MC908AZ32ACFU Freescale Semiconductor, MC908AZ32ACFU Datasheet - Page 99

• Manufacturer Part Number: MC908AZ32ACFU
• Description: IC MCU 32K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ32ACFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate the MCU clocks. CGMOUT is
a 50% duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be
either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.
8.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the CPU interrupt signal generated by the PLL lock detector.
8.5 CGM Registers
Three registers control and monitor operation of the CGM:
8.5.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the on/off switch, and the base clock
selector bit.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Flag Bit
Freescale Semiconductor
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This read/write bit enables the PLL to generate a CPU interrupt request when the LOCK bit toggles,
setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the
PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF
bit.
1 = PLL CPU interrupt requests enabled
0 = PLL CPU interrupt requests disabled
1 = Change in lock condition
0 = No change in lock condition
PLL control register (PCTL)
PLL bandwidth control register (PBWC)
PLL programming register (PPG)
Address:
Do not inadvertently clear the PLLF bit. Be aware that any read or
read-modify-write operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
$001C
PLLIE
Bit 7
0
Figure 8-4. PLL Control Register (PCTL)
= Unimplemented
PLLF
6
0
MC68HC908AZ32A Data Sheet, Rev. 2
PLLON
5
1
NOTE
BCS
4
0
3
1
1
2
1
1
1
1
1
Bit 0
1
1
CGM Registers
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