HD64F2319EVTE25 Renesas Electronics America, HD64F2319EVTE25 Datasheet - Page 140
HD64F2319EVTE25
Manufacturer Part Number
HD64F2319EVTE25
Description
IC H8S MCU FLASH 512K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2319EVTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2319EVTE25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64F2319EVTE25V
Manufacturer:
RENESAS
Quantity:
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Section 4 Exception Handling
4.5
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Interrupt Control Mode
0
2
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
4.6
Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
Rev.7.00 Feb. 14, 2007 page 106 of 1108
REJ09B0089-0700
Trap Instruction
Stack Status after Exception Handling
SP
Figure 4.4 Stack Status after Exception Handling (Advanced Modes)
Status of CCR and EXR after Trap Instruction Exception Handling
Note: * Ignored on return.
(a) Interrupt control mode 0
(24 bits)
CCR
PC
I
1
1
CCR
—
—
UI
SP
(b) Interrupt control mode 2
I2 to I0
—
—
(24 bits)
Reserved*
EXR
CCR
PC
EXR
T
—
0
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