HD64F2319EVTE25 Renesas Electronics America, HD64F2319EVTE25 Datasheet - Page 209
HD64F2319EVTE25
Manufacturer Part Number
HD64F2319EVTE25
Description
IC H8S MCU FLASH 512K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2319EVTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2319EVTE25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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HD64F2319EVTE25V
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RENESAS
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Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.18.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
Address bus
CS (area A)
CS (area B)
RD
Possibility of overlap between
CS (area B) and RD
φ
Figure 6.18 Relationship between Chip Select (CS) and Read (RD)
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS1 = 0)
T
2
T
3
Bus cycle B
T
1
T
2
Address bus
CS (area A)
CS (area B)
Rev.7.00 Feb. 14, 2007 page 175 of 1108
RD
φ
T
1
Bus cycle A
(b) Idle cycle inserted
T
(ICIS1 = 1 (initial value))
2
Section 6 Bus Controller
T
3
REJ09B0089-0700
T
I
Bus cycle B
T
1
T
2
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