HD64F2319EVTE25 Renesas Electronics America, HD64F2319EVTE25 Datasheet - Page 601
HD64F2319EVTE25
Manufacturer Part Number
HD64F2319EVTE25
Description
IC H8S MCU FLASH 512K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2319EVTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Quantity:
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17.2.2
Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the
EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L
(BCRL).
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF *
to be internal addresses or external addresses.
Bit 5
EAE
0
1
Notes: 1. The reserved area must not be accessed.
17.3
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) and the EAE
bit in BCRL. These settings are shown in table 17.2 and table 17.3.
Bit
Initial value :
R/W
2. H'010000 to H'03FFFF in the H8S/2318.
3. H8S/2317S in mask ROM version.
Bus Control Register L (BCRL)
Operation
H8S/2319, H8S/2319C,
H8S/2318, H8S/2315,
H8S/2314
On-chip ROM
Addresses H'010000 to H'03FFFF *
mode) or a reserved area *
H'010000 to H'05FFFF in the H8S/2315 and H8S/2314.
H'010000 to H'07FFFF in the H8S/2319 and H8S/2319C.
:
:
BRLE
R/W
7
0
BREQOE
R/W
6
0
H8S/2317(S) *
Addresses H'010000 to H'01FFFF
are in on-chip ROM and addresses
H'020000 to H'03FFFF are a reserved
area *
1
(in single-chip mode)
EAE
R/W
1
5
1
2
are external addresses (in external expanded
Description
3
R/W
—
4
1
Rev.7.00 Feb. 14, 2007 page 567 of 1108
R/W
—
3
1
R/W
—
2
1
H8S/2316S
Reserved area *
REJ09B0089-0700
Section 17 ROM
R/W
—
1
0
(Initial value)
WAITE
R/W
1
0
0
2
are
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