HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 475
HD64F2378RVFQ33
Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2378RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Auto Request/Burst Mode/Normal Transfer Mode: When the EDA bit is set to 1 in EDMDR,
an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it
continues (as a burst) until the transfer end condition is satisfied.
If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another
bus master.
Transfer requests for other channels are held pending until the end of transfer on the current
channel.
Figures 8.31 to 8.34 show operation timing examples for various conditions.
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
φ pin
Bus cycle
CPU
operation
CPU cycle CPU cycle
CPU cycle CPU cycle
External
External
1
space
space
Figure 8.31 Auto Request/Burst Mode/Normal Transfer Mode
Figure 8.32 Auto Request/Burst Mode/Normal Transfer Mode
External
External
space
space
(CPU Cycles/Dual Address Mode/BGUP = 0)
(CPU Cycles/Dual Address Mode/BGUP = 1)
External
EXDMA
External
EXDMA
space
space
read
read
EXDMA
EXDMA
write
write
1 bus cycle
CPU cycle
EXDMA
read
External
EXDMA
EXDMA
Rev.7.00 Mar. 18, 2009 page 407 of 1136
space
write
read
Section 8 EXDMA Controller (EXDMAC)
Repeated
EXDMA
write
1 bus cycle
CPU cycle
Last transfer cycle
EXDMA
read
REJ09B0109-0700
EXDMA
EXDMA
write
read
CPU cycle
EXDMA
0
write
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