HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 713
HD64F2378RVFQ33
Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2378RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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12.4.4
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
Figure 12.6 illustrates the non-overlapping pulse output operation.
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 12.7 shows the timing of this operation.
if their value is 1.
Pulse
output
pin
Non-Overlapping Pulse Output
DDR
Figure 12.6 Non-Overlapping Pulse Output
Normal output/inverted output
Q
NDER
Q
PODR
C
Section 12 Programmable Pulse Generator (PPG)
D
Rev.7.00 Mar. 18, 2009 page 645 of 1136
Q
NDR
Compare match A
Compare match B
D
Internal data bus
REJ09B0109-0700
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