HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 800
HD64F2378RVFQ33
Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2378RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
- Current page: 800 of 1208
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Section 15 Serial Communication Interface (SCI, IrDA)
Rev.7.00 Mar. 18, 2009 page 732 of 1136
REJ09B0109-0700
No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
PER ∨ FER ∨ ORER = 1?
Clear RE bit in SCR to 0
Read RDRF flag in SSR
Read ORER, PER, and
Figure 15.9 Sample Serial Reception Data Flowchart (1)
All data received?
FER flags in SSR
Start of reception
Initialization
RDRF = 1?
<End>
Yes
Yes
No
(Continued on next page)
Error handling
Yes
[1]
[2]
[4]
[5]
[3]
[1]
[2] [3]
[4]
[5]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
break detection:
If a receive error occurs, read the
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
processing, ensure that the
ORER, PER, and FER flags are
all cleared to 0. Reception cannot
be resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
the input port corresponding to
the RxD pin.
SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DMAC or DTC is
activated by an RXI interrupt and
the RDR value is read.
Receive error handling and
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