HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet
HD64F2623FA20J
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HD64F2623FA20J Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2626 Group, H8S/2623 Group, H8S/2626F-ZTAT 16 H8S/2623F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as ...
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Rev. 5.00 Jan 10, 2006 page iv of xxiv ...
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The H8S/2626 Group and H8S/2623 Group are series of high-performance microcontrollers with a 32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system configuration. The H8S/2600 CPU can execute basic instructions in one state, and is ...
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Rev. 5.00 Jan 10, 2006 page vi of xxiv ...
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Main Revisions in This Edition Item Page Revision (See Manual for Details) All — 19.13 Flash 682 Figure 19.26 amended Memory Programming and Erasing Precautions Figure 19.26 Power-On/Off Timing (Boot VCC Mode) FWE MD2 to MD0 RES SWE1 bit All ...
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Item Page Revision (See Manual for Details) 19.13 Flash 683 Figure 19.27 amended Memory Programming and Erasing Precautions Figure 19.27 Power-On/Off Timing (User VCC Program Mode) FWE MD2 to MD0 RES SWE1 bit Figure 19.28 684 Figure 19.28 amended Mode ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Descriptions ................................................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 10 1.3.3 Pin Functions ....................................................................................................... 18 Section 2 CPU ...................................................................................................................... 23 2.1 Overview........................................................................................................................... 23 ...
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Bus-Released State............................................................................................... 65 2.8.6 Power-Down State ............................................................................................... 65 2.9 Basic Timing ..................................................................................................................... 66 2.9.1 Overview.............................................................................................................. 66 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 66 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 68 2.9.4 On-Chip HCAN Module Access Timing ............................................................. 70 ...
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Notes on Use of the Stack ................................................................................................. 95 Section 5 Interrupt Controller 5.1 Overview........................................................................................................................... 97 5.1.1 Features................................................................................................................ 97 5.1.2 Block Diagram ..................................................................................................... 98 5.1.3 Pin Configuration................................................................................................. 99 5.1.4 Register Configuration......................................................................................... 99 5.2 Register Descriptions ........................................................................................................ 100 5.2.1 System Control ...
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Break Address Register B (BARB)...................................................................... 130 6.2.3 Break Control Register A (BCRA) ...................................................................... 130 6.2.4 Break Control Register B (BCRB)....................................................................... 132 6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 132 6.3 Operation .......................................................................................................................... 133 6.3.1 PC Break Interrupt Due to ...
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Idle Cycle .......................................................................................................................... 174 7.6.1 Operation ............................................................................................................. 174 7.6.2 Pin States in Idle Cycle ........................................................................................ 176 7.7 Write Data Buffer Function .............................................................................................. 177 7.8 Bus Release....................................................................................................................... 178 7.8.1 Overview.............................................................................................................. 178 7.8.2 Operation ............................................................................................................. 178 7.8.3 Pin States in External ...
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Number of DTC Execution States........................................................................ 207 8.3.11 Procedures for Using DTC................................................................................... 209 8.3.12 Examples of Use of the DTC ............................................................................... 210 8.4 Interrupts ........................................................................................................................... 213 8.5 Usage Notes ...................................................................................................................... 213 Section 9 I/O Ports .............................................................................................................. 215 9.1 Overview........................................................................................................................... 215 ...
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Overview.............................................................................................................. 274 9.9.2 Register Configuration......................................................................................... 275 9.9.3 Pin Functions ....................................................................................................... 277 9.9.4 MOS Input Pull-Up Function............................................................................... 278 9.10 Port F................................................................................................................................. 279 9.10.1 Overview.............................................................................................................. 279 9.10.2 Register Configuration......................................................................................... 280 9.10.3 Pin Functions ....................................................................................................... 282 Section 10 16-Bit Timer Pulse Unit ...
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Operation Timing.............................................................................................................. 354 10.6.1 Input/Output Timing ............................................................................................ 354 10.6.2 Interrupt Signal Timing........................................................................................ 358 10.7 Usage Notes ...................................................................................................................... 362 Section 11 Programmable Pulse Generator (PPG) 11.1 Overview........................................................................................................................... 373 11.1.1 Features................................................................................................................ 373 11.1.2 Block Diagram ..................................................................................................... 374 11.1.3 Pin Configuration................................................................................................. 375 ...
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Operation .......................................................................................................................... 412 12.3.1 Watchdog Timer Operation ................................................................................. 412 12.3.2 Interval Timer Operation ..................................................................................... 415 12.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 415 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 416 12.4 Interrupts ........................................................................................................................... ...
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Features................................................................................................................ 491 14.1.2 Block Diagram ..................................................................................................... 492 14.1.3 Pin Configuration................................................................................................. 493 14.1.4 Register Configuration......................................................................................... 494 14.2 Register Descriptions ........................................................................................................ 495 14.2.1 Smart Card Mode Register (SCMR) .................................................................... 495 14.2.2 Serial Status Register (SSR) ................................................................................ 496 14.2.3 Serial Mode Register ...
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Transmit Error Counter (TEC)............................................................................. 549 15.2.16 Unread Message Status Register (UMSR) ........................................................... 550 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 551 15.2.18 Message Control (MC0 to MC15) ....................................................................... 553 15.2.19 Message Data (MD0 to MD15) ........................................................................... 557 15.2.20 Module ...
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Block Diagram ..................................................................................................... 614 17.1.3 Pin Configuration................................................................................................. 615 17.1.4 Register Configuration......................................................................................... 615 17.2 Register Descriptions ........................................................................................................ 616 17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3) ................................................. 616 17.2.2 D/A Control Register 23 (DACR23).................................................................... 616 17.2.3 Module Stop Control ...
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Program Mode ..................................................................................................... 651 19.7.2 Program-Verify Mode.......................................................................................... 652 19.7.3 Erase Mode .......................................................................................................... 656 19.7.4 Erase-Verify Mode .............................................................................................. 656 19.8 Protection .......................................................................................................................... 658 19.8.1 Hardware Protection ............................................................................................ 658 19.8.2 Software Protection.............................................................................................. 659 19.8.3 Error Protection.................................................................................................... 660 19.9 Flash Memory Emulation ...
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Section 21A Power-Down Modes [H8S/2623 Group] 21A.1 Overview ....................................................................................................................... 699 21A.1.1 Register Configuration.................................................................................. 702 21A.2 Register Descriptions..................................................................................................... 702 21A.2.1 Standby Control Register (SBYCR) ............................................................. 702 21A.2.2 System Clock Control Register (SCKCR) .................................................... 704 21A.2.3 Low-Power Control Register (LPWRCR) .................................................... 705 ...
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Module Stop Mode ....................................................................................... 728 21B.5.2 Usage Notes .................................................................................................. 730 21B.6 Software Standby Mode ................................................................................................ 730 21B.6.1 Software Standby Mode................................................................................ 730 21B.6.2 Clearing Software Standby Mode................................................................. 730 21B.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode............................................................................................... 731 21B.6.4 ...
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Appendix A Instruction Set A.1 Instruction List .................................................................................................................. 763 A.2 Instruction Codes .............................................................................................................. 787 A.3 Operation Code Map......................................................................................................... 802 A.4 Number of States Required for Instruction Execution ...................................................... 806 A.5 Bus States during Instruction Execution ........................................................................... 817 A.6 Condition Code ...
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Overview The H8S/2626 Group and H8S/2623 Group are series of microcomputers (MCUs) that integrate peripheral functions required for system configuration together with an H8S/2600 CPU employing an original Renesas architecture. The H8S/2600 CPU has an internal 32-bit architecture, is ...
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Section 1 Overview Table 1.1 Overview Item Specifications CPU General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum operating frequency: 20 MHz High-speed arithmetic operations 8/16/32-bit ...
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Item Specifications Data transfer Can be activated by internal interrupt or software controller (DTC) Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to ...
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Section 1 Overview Item Specifications D/A converter Resolution: 8 bits (H8S/2626 Group Output: 2 channels only) I/O ports 51 input/output pins, 17 input-only pins (H8S/2626 Group) I/O ports 53 input/output pins, 17 input-only pins (H8S/2623 Group) Memory Flash memory or ...
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Item Specifications Operating modes Four MCU operating modes Mode Clock pulse Built-in PLL circuit ( generator Input clock frequency MHz Package 100-pin plastic QFP (FP-100B) Product lineup Mask ROM Version ...
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Section 1 Overview 1.2 Internal Block Diagram Figures 1.1 and 1.2 show internal block diagrams of the H8S/2623 Group and H8S/2626 Group. MD2 MD1 MD0 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI * FWE PF7/ PF6/AS PF5/RD PF4/HWR ...
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MD2 MD1 MD0 OSC1 OSC2 EXTAL XTAL PLLVCC PLLCAP PLLVSS STBY RES WDTOVF NMI FWE * PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF2/WAIT/BREQO PF1/BACK PF0/BREQ/IRQ2 Port 1 Note: * The FWE pin is provided in the flash memory version only. Figure ...
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Section 1 Overview 1.3 Pin Descriptions 1.3.1 Pin Arrangement Figures 1.3 and 1.4 show pin arrangements of the H8S/2623 Group and H8S/2626 Group. AVCC 76 Vref 77 P40/AN0 78 P41/AN1 79 P42/AN2 80 P43/AN3 81 P44/AN4 82 P45/AN5 83 P46/AN6 ...
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AVCC 76 Vref 77 P40/AN0 78 P41/AN1 79 P42/AN2 80 P43/AN3 81 P44/AN4 82 P45/AN5 83 P46/AN6 84 P47/AN7 85 P90/AN8 86 P91/AN9 87 P92/AN10 88 P93/AN11 89 90 P94/AN12 P95/AN13 91 P96/AN14/DA2 92 93 P97/AN15/DA3 94 AVSS VSS 95 ...
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Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Tables 1.2 and 1.3 show the pin functions in each of the operating modes of the H8S/2623 Group and H8S/2626 Group. Table 1.2 Pin Functions in Each Operating Mode Pin ...
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Pin No. FP-100B Mode 4 23 D11 24 D12 25 D13 26 D14 27 D15 PB0/A8/TIOCA3 37 VSS 38 PB1/A9/TIOCB3 39 PVCC2 40 ...
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Section 1 Overview Pin No. FP-100B Mode 4 54 VSS 55 MD1 56 MD2 57 PLLVSS 58 PLLCAP 59 PLLVCC RES 60 61 NMI STBY 62 63 VCC 64 XTAL 65 VSS 66 EXTAL 67 FWE 68 PF7 ...
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Pin No. FP-100B Mode 4 84 P46/AN6 85 P47/AN7 86 P90/AN8 87 P91/AN9 88 P92/AN10 89 P93/AN11 90 P94/AN12 91 P95/AN13 92 P96/AN14 93 P97/AN15 94 AVSS 95 VSS WDTOVF 96 97 PVCC4 98 P10/PO8/TIOCA0/ A20 99 P11/PO9/TIOCB0/ A21 100 ...
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Section 1 Overview Table 1.3 Pin Functions in Each Operating Mode Pin No. FP-100B Mode 4 1 P13/PO11/TIOCD0/ TCLKB/A23 2 P14/PO12/TIOCA1/ IRQ0 3 P15/PO13/TIOCB1/ TCLKC 4 P16/PO14/TIOCA2/ IRQ1 5 P17/PO15/TIOCB2/ TCLKD 6 VCC 7 HTxD 8 VSS 9 HRxD 10 ...
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Pin No. FP-100B Mode 4 27 D15 PB0/A8/TIOCA3 37 VSS 38 PB1/A9/TIOCB3 39 PVCC2 40 PB2/A10/TIOCC3 41 PB3/A11/TIOCD3 42 PB4/A12/TIOCA4 43 PB5/A13/TIOCB4 44 ...
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Section 1 Overview Pin No. FP-100B Mode 4 58 PLLCAP 59 PLLVCC RES 60 61 NMI STBY 62 63 VCC 64 XTAL 65 VSS 66 EXTAL 67 FWE 68 PF7 HWR 71 72 PF3/LWR/ADTRG/ IRQ3 73 ...
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Pin No. FP-100B Mode 4 88 P92/AN10 89 P93/AN11 90 P94/AN12 91 P95/AN13 92 P96/AN14/DA2 93 P97/AN15/DA3 94 AVSS 95 VSS WDTOVF 96 97 PVCC4 98 P10/PO8/TIOCA0/ A20 99 P11/PO9/TIOCB0/ A21 100 P12/PO10/TIOCC0/ TCLKA/A22 Note: NC pins should be connected ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.4 summarizes the pin functions. Table 1.4 Pin Functions Type Symbol Power supply VCC PVCC1 PVCC2 PVCC3 PVCC4 VSS Clock PLLVCC PLLVSS PLLCAP XTAL EXTAL OSC1 * 1 OSC2 * 1 Rev. 5.00 ...
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Type Symbol Operating MD2 to mode control MD0 RES System control STBY BREQ BREQO BACK FWE Interrupts NMI IRQ5 to IRQ0 Address bus A23 to A0 I/O Pin Name Input Mode pins Input Reset input When this pin is driven ...
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Section 1 Overview Type Symbol Data bus D15 Bus control RD HWR LWR WAIT 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, ...
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Type Symbol Programmable PO15 to pulse PO8 generator (PPG) WDTOVF Watchdog timer (WDT) Serial TxD2, communication TxD1, interface (SCI)/ TxD0 smart card RxD2, interface RxD1, RxD0 SCK2, SCK1, SCK0 Controller HTxD area network (HCAN) HRxD A/D converter AN15 to AN0 ...
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Section 1 Overview Type Symbol I/O ports P17 to P10 P47 to P40 P97 to P90 PA5 to PA0 * 2 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF0 Notes: 1. Applies to ...
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Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8/16/32-bit register-register add/subtract 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: ...
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In addition, there are differences in address space, CCR and EXR register functions, power-down modes, etc., depending on the model. 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements. More general ...
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Section 2 CPU Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. Higher speed Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: ...
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Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) ...
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Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. Stack Structure: In advanced mode, when the program counter (PC) ...
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Address Space Figure 2.6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC). (1) Program Counter (PC) This 24-bit counter indicates the ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The and C flags are used as branching conditions for conditional branch (Bcc) instructions. (4) Multiply-Accumulate Register ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * 1 , PUSH * ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL BWL transfer POP, PUSH — LDM, ...
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Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source ...
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Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Size * 1 Function B/W/L (EAs) Rd, Rs Moves data between two general registers or between a general register and memory, or moves ...
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Section 2 CPU Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Rev. 5.00 Jan 10, 2006 page 44 of 1042 REJ09B0275-0500 Size * 1 Function B/W/L Rd ± Rs Rd, Rd ...
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Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS MAC CLRMAC LDMAC STMAC Size * 1 Function B/W Rd ÷ Performs signed division on data in two general registers: either 16 bits ÷ 8 bits remainder or ...
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Section 2 CPU Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Rev. 5.00 Jan 10, 2006 page 46 of 1042 REJ09B0275-0500 Size * 1 Function B/W Rd, Rd ...
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Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR Size * 1 Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified ...
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Section 2 CPU Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Rev. 5.00 Jan 10, 2006 page 48 of 1042 REJ09B0275-0500 Size * 1 Function B C (<bit-No.> of <EAd>) Exclusive-ORs the carry flag with a specified ...
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Type Instruction Branch Bcc instructions JMP BSR JSR RTS Size * 1 Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description BRA(BT) Always (true) BRN(BF) Never (false) BHI ...
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Section 2 CPU Type Instruction System TRAPA control RTE instructions SLEEP LDC STC ANDC ORC XORC NOP Rev. 5.00 Jan 10, 2006 page 50 of 1042 REJ09B0275-0500 Size * 1 Function — Starts trap-instruction exception handling. — Returns from an ...
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Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.4 Basic ...
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Section 2 CPU Figure 2.12 shows examples of instruction formats. (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Section 2 CPU (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives ...
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Table 2.5 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: * Not available in the H8S/2626 Group or H8S/2623 Group. (6) Immediate—#xx:8, #xx:16, or ...
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Section 2 CPU Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2626 Group or H8S/2623 Group. Specified Branch ...
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Table 2.6 Effective Address Calculation Section 2 CPU Rev. 5.00 Jan 10, 2006 page 57 of 1042 REJ09B0275-0500 ...
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Section 2 CPU Rev. 5.00 Jan 10, 2006 page 58 of 1042 REJ09B0275-0500 ...
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Section 2 CPU Rev. 5.00 Jan 10, 2006 page 59 of 1042 REJ09B0275-0500 ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 ...
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Bus-released state Exception handling state RES= High Reset state * 1 Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition can also be made to ...
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Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES pin goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When ...
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Section 2 CPU *2 Normal mode SP CCR *1 CCR PC (16 bits) (a) Interrupt control mode 0 Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. Ignored when returning. 2. Not available in the ...
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Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than ...
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Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred "state." The memory ...
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Bus cycle Address bus Retained AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.18 Pin States during On-Chip Memory Access T1 Rev. 5.00 Jan 10, 2006 page 67 of 1042 Section 2 CPU REJ09B0275-0500 ...
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Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 ...
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Address bus AS RD HWR, LWR Data bus Figure 2.20 Pin States during On-Chip Supporting Module Access Cycle Bus cycle T1 T2 Retained High High High High-impedance state Rev. 5.00 Jan 10, 2006 page 69 of 1042 Section 2 CPU ...
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Section 2 CPU 2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip ...
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Internal address bus HCAN read signal Read Internal data bus HCAN write signal Write Internal data bus Figure 2.22 On-Chip HCAN Module Access Cycle (Wait States Inserted) Address bus AS RD HWR, LWR Data bus Figure 2.23 Pin States in ...
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Section 2 CPU 2.9.5 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8S/2626 Group and H8S/2623 Group have four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the ...
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Section 3 MCU Operating Modes Note that the functions of each pin depend on the operating mode. The H8S/2626 Group and H8S/2623 Group can be used only in modes This means that the mode pins must be ...
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Register Descriptions 3.2.1 Mode Control Register (MDCR) Bit : 7 — Initial value : 1 R/W : R/W Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit register that indicates the current operating mode of the ...
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Section 3 MCU Operating Modes Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the MAC instruction. Bit 7 MACS Description 0 Non-saturating calculation for MAC instruction 1 Saturating calculation for MAC instruction Bit 6—Reserved: This bit is ...
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Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released not initialized in software standby mode. Bit 0 RAME Description 0 On-chip RAM is disabled 1 On-chip ...
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Section 3 MCU Operating Modes Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 ...
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Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports and C, function as an address bus, ports D and E function as ...
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Section 3 MCU Operating Modes All I/O ports are available for use as input-output ports. 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 and vary depending on the operating mode. Table 3.3 ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFB000 Reserved area H'FFC000 On-chip RAM * H'FFEFC0 External area H'FFF800 Internal I/O registers H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM * ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFB000 Reserved area H'FFD000 On-chip RAM * H'FFEFC0 External area H'FFF800 Internal I/O registers H'FFFF40 External area H'FFFF60 Internal I/O ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFB000 Reserved area H'FFE000 On-chip RAM * H'FFEFC0 External area H'FFF800 Internal I/O registers H'FFFF40 External area H'FFFF60 Internal I/O registers H'FFFFC0 On-chip RAM * ...
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Section 3 MCU Operating Modes Rev. 5.00 Jan 10, 2006 page 84 of 1042 REJ09B0275-0500 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Reset Manual reset * 3 Reserved Trace Direct transitions * 4 (H8S/2626 only) External interrupt NMI Trap instruction (4 sources) Reserved External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved Internal interrupt * ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2626 Group or H8S/2623 Group enters the reset state. A reset initializes the internal ...
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RES Address bus RD HWR, LWR D15 to D0 (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = ...
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Section 4 Exception Handling RES Internal address bus Internal read signal Internal write signal Internal data bus (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception ...
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Register reading and writing is enabled when module stop mode is exited. 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, ...
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Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (H8S/2626 Group: 48, H8S/2623 Group: 47) in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figures 4.5 (1) and 4.5 (2) show the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR * PC (16 bits) (a) Interrupt control ...
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Notes on Use of the Stack When accessing word data or longword data, the H8S/2626 Group or H8S/2623 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword ...
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Section 4 Exception Handling Rev. 5.00 Jan 10, 2006 page 96 of 1042 REJ09B0275-0500 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2626 Group and H8S/2623 Group control interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Any of two interrupt control modes can ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request SWDTEND to SLE0 ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ5 to IRQ0 External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers of ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 MACS Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Priority Registers (IPRA to IPRK, IPRM) Bit : 7 — IPR6 Initial value : 0 R/W : — R/W The IPR registers are twelve 8-bit readable/writable registers that set priorities (levels ...
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Section 5 Interrupt Controller Table 5.3 Correspondence between Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK IPRM Notes: 1. Reserved bits. These bits are always read as 1 and cannot be ...
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IRQ Enable Register (IER) Bit : 7 — Initial value : 0 R/W : R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ5 to IRQ0. IER is initialized to H'00 by ...
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Section 5 Interrupt Controller 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 — Initial value : 0 R/W : R/W R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA Initial value : 0 R/W : R/W ...
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IRQ Status Register (ISR) Bit : 7 — Initial value : 0 R/(W) * R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status ...
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Section 5 Interrupt Controller Bit n IRQnF Description 0 [Clearing conditions] (Initial value) Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB ...
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IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5 to IRQ0. Interrupts IRQ5 to IRQ0 have the following features: Using ISCR possible to select whether an interrupt is generated by ...
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Section 5 Interrupt Controller Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved SWDTEND (software activation interrupt end) WOVI0 (interval timer) Reserved PC break ADI (A/D conversion end) WOVI1 (interval timer) (H8S/2626 Group only) ...
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Section 5 Interrupt Controller Interrupt Source TGI1A (TGR1A input capture/ compare match) TGI1B (TGR1B input capture/ compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/ compare match) TGI2B (TGR2B input capture/ compare match) TCI2V (overflow 2) TCI2U ...
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Interrupt Source TGI5A (TGR5A input capture/ compare match) TGI5B (TGR5B input capture/ compare match) TCI5V (overflow 5) TCI5U (underflow 5) Reserved ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive ...
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Section 5 Interrupt Controller Interrupt Source ERS0 OVR0 RM0 RM1 SLE0 Note: * Lower 16 bits of the start address. 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2626 Group and H8S/2623 Group differ ...
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Table 5.5 Interrupt Control Modes SYSCR Interrupt Control Mode INTM1 INTM0 — — 1 Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt ...
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Section 5 Interrupt Controller (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.6 shows the interrupts selected in each interrupt control mode. Table 5.6 Interrupts Selected in Each ...
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Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the ...
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Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit ...
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Program execution status Interrupt generated? Yes No IRQ0 Yes Save PC and CCR Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Section 5 Interrupt Controller No ...
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Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. ...
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Program execution status Interrupt generated? Yes No Level 7 interrupt? Yes Level 6 interrupt? No Mask level 6 or below? Yes Mask level 5 Save PC, CCR, and EXR Clear T bit to 0 Update mask level Read vector address ...
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Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Interrupt Response Times The H8S/2626 Group and H8S/2623 Group are capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5.9 ...
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Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch Branch address read Stack manipulation Legend: m: Number of wait states in an external device access. 5.5 Usage Notes 5.5.1 Contention between ...
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TIER0 write cycle by CPU Internal address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared ...
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Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the ...
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Block Diagram Figure 5.9 shows a block diagram of the DTC interrupt controller. Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Interrupt controller Figure 5.9 Interrupt Control for DTC 5.6.3 Operation The interrupt controller has three ...
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Section 5 Interrupt Controller (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector Table, for the respective priorities. ...
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Section 6 PC Break Controller (PBC) 6.1 Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without ...
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Section 6 PC Break Controller (PBC) 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the PC break controller. BARA Comparator Internal address Access status Comparator BARB Figure 6.1 Block Diagram of PC Break Controller Rev. 5.00 Jan 10, ...
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Register Configuration Table 6.1 shows the PC break controller registers. Table 6.1 PC Break Controller Registers Name Break address register A Break address register B Break control register A Break control register B Module stop control register C Notes: ...
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Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) 7 Bit CMFA Initial value ...
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Bits 5 to 3—Break Address Mask Register (BAMRA2 to BAMRA0): These bits specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description ...
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Section 6 PC Break Controller (PBC) Bit 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts. Bit 0 BIEA Description 0 PC break interrupts are disabled 1 PC break interrupts are enabled 6.2.4 Break Control Register ...
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Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of ...
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Section 6 PC Break Controller (PBC) 6.3.2 PC Break Interrupt Due to Data Access (1) Initial settings Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external ...
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Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. (1) When the SLEEP instruction causes a transition from high-speed ...
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Section 6 PC Break Controller (PBC) SLEEP instruction SLEEP instruction execution PC break exception System clock handling Execution of instruction Direct transition after sleep instruction exception handling (A) PC break exception Execution of instruction after sleep instruction Note: * Supported ...
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When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. (1) When the PBC is enabled (i.e. when the break interrupt enable bit is set ...
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Section 6 PC Break Controller (PBC) 6.3.7 Additional Notes (1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address ...
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Section 7 Bus Controller 7.1 Overview The H8S/2626 Group and H8S/2623 Group have an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, ...
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Section 7 Bus Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the bus controller. External bus control signals BREQ BACK BREQO WAIT Legend: ABWCR: Bus width control register ASTCR: Access state control register BCRH: Bus control register ...
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Pin Configuration Table 7.1 summarizes the pins of the bus controller. Table 7.1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write LWR Low write WAIT Wait BREQ Bus request BACK Bus request acknowledge BREQO ...
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Section 7 Bus Controller 7.1.4 Register Configuration Table 7.2 summarizes the registers of the bus controller. Table 7.2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control ...
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Register Descriptions 7.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : 1 R/W : R/W Mode 4 Initial value : 0 R/W : R/W ABWCR is an 8-bit readable/writable register ...
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Section 7 Bus Controller 7.2.2 Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal ...
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Section 7 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Section 7 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bus Control Register H (BCRH) Bit : 7 ICIS1 ICIS0 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. ...
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Section 7 Bus Controller Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. Bit 5 BRSTRM Description 0 Area 0 is basic bus interface 1 Area 0 is burst ROM interface Bit 4—Burst ...
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Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, enabling or disabling of the write data ...
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Section 7 Bus Controller Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle. Bit 1 WDBE Description 0 Write data buffer function not used 1 Write data buffer ...
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When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1. Bit 3 Bit 2 Bit 1 Bit 0 AE3 AE2 AE1 AE0 ...
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Section 7 Bus Controller 7.3 Overview of Bus Control 7.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 2-Mbyte units, and performs bus control for external space ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Section 7 Bus Controller Table 7.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 0 0 — — 7.3.3 Memory Interfaces The H8S/2626 Group and ...
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Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and ...
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Section 7 Bus Controller 7.4 Basic Bus Interface 7.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7.3). 7.4.2 Data ...
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Access Space: Figure 7.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of ...
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Section 7 Bus Controller 7.4.3 Valid Strobes Table 7.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data ...
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Basic Timing 8-Bit 2-State Access Space: Figure 7.5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR ...
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Section 7 Bus Controller 8-Bit 3-State Access Space: Figure 7.6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The ...
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Access Space: Figures 7.7 to 7.9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, ...
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Section 7 Bus Controller Address bus AS RD D15 to D8 Read HWR LWR Write D15 Figure 7.8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev. 5.00 ...
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Address bus AS RD D15 to D8 Read HWR LWR Write D15 Figure 7.9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Section 7 Bus Controller Bus cycle T T ...
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Section 7 Bus Controller 16-Bit 3-State Access Space: Figures 7.10 to 7.12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is ...
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Address bus AS RD D15 to D8 Read HWR LWR Write D15 Figure 7.11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Bus cycle ...
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Section 7 Bus Controller Address bus AS RD D15 to D8 Read HWR LWR Write D15 Figure 7.12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev. 5.00 Jan 10, ...
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Wait Control When accessing external space, the H8S/2626 Group or H8S/2623 Group can extend the bus cycle by inserting one or more wait states (T wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From ...
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Section 7 Bus Controller Figure 7.13 shows an example of wait state insertion timing. WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus indicates the timing of WAIT pin sampling. Note: Figure 7.13 Example of Wait ...
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Burst ROM Interface 7.5.1 Overview With the H8S/2626 Group and H8S/2623 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM ...
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Section 7 Bus Controller Full access T 1 Address bus AS RD Data bus Figure 7.14 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev. 5.00 Jan 10, 2006 page 172 of 1042 REJ09B0275-0500 T ...
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Address bus AS RD Data bus Figure 7.14 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the ...
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Section 7 Bus Controller 7.6 Idle Cycle 7.6.1 Operation When the H8S/2626 Group or H8S/2623 Group accesses external space , it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read ...