HD64F2623FA20J Renesas Electronics America, HD64F2623FA20J Datasheet - Page 306
HD64F2623FA20J
Manufacturer Part Number
HD64F2623FA20J
Description
IC H8S MCU FLASH 256K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2623FA20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 9 I/O Ports
9.10.2
Table 9.21 shows the port F register configuration.
Table 9.21 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
Modes 4 to 6
Mode 7
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to
H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used
to select whether the bus control output pins retain their output state or become high-impedance
when a transition is made to software standby mode.
Rev. 5.00 Jan 10, 2006 page 280 of 1042
REJ09B0275-0500
Bit
Initial value :
R/W
Initial value :
R/W
Modes 4 to 6
Pin PF7 functions as the output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK,
2. Initial value depends on the mode.
Register Configuration
:
:
:
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
W
W
7
1
0
W
W
6
0
0
Abbreviation
PFDDR
PFDR
PORTF
W
W
5
0
0
W
W
4
0
0
R/W
W
R/W
R
W
W
3
0
0
Initial Value
H'80/H'00 *
H'00
Undefined
W
W
2
0
0
2
W
W
1
0
0
H'FFBE
Address *
H'FE3E
H'FF0E
W
W
0
0
0
1
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