HD64F3694FY Renesas Electronics America, HD64F3694FY Datasheet - Page 106
HD64F3694FY
Manufacturer Part Number
HD64F3694FY
Description
IC H8 MCU FLASH 32K 48-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.HD64F3694GFYV.pdf
(452 pages)
Specifications of HD64F3694FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3694FYJV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F3694FYV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Power-Down Modes
6.1.1
SYSCR1 controls the power-down modes, as well as SYSCR2.
Rev.5.00 Nov. 02, 2005 Page 76 of 418
REJ09B0028-0500
Bit
7
6
5
4
3
2 to 0
Bit Name
SSBY
STS2
STS1
STS0
NESEL
System Control Register 1 (SYSCR1)
Initial
Value
0
0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: a transition is made to sleep mode or subsleep mode.
1: a transition is made to standby mode.
For details, see table 6.2.
Standby Timer Select 2 to 0
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting from
standby mode, subactive mode, or subsleep mode to
active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms. The
relationship between the specified value and the number
of wait states is shown in table 6.1. When an external
clock is to be used, the minimum value (STS2 = STS1 =
STS0 = 1) is recommended.
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (
generates the oscillator clock (
sampling frequency of the oscillator clock when the watch
clock signal (
clear NESEL to 0.
0: Sampling rate is
1: Sampling rate is
Reserved
These bits are always read as 0.
W
) and the system clock pulse generator
W
) is sampled. When
OSC
OSC
/16
/4
OSC
). This bit selects the
OSC
= 4 to 20 MHz,
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