HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 107
HD6417020SVX12I
Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12I
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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6.5
6.5.1
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on
the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
6.5.2
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF
2. TRAPA instruction, branch taken: TRAPA
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that does an overrun fetch.
When the next instruction or the one after that is set as a break condition, a branch will result in
the generation of a user break interrupt at the next instruction or the instruction after that, neither
of which instructions will be executed.
86 RENESAS
Instruction fetch cycles: Conditional branch fetch
instruction overrun fetch
Instruction execution: Conditional branch instruction execution
instruction execution
Instruction fetch cycles: TRAPA instruction fetch
instruction overrun fetch
Instruction execution: TRAPA instruction execution
execution
Notes
On-Chip Memory Instruction Fetch
Instruction Fetch at Branches
Branch destination fetch
Branch destination fetch
Next-instruction overrun fetch
Next-instruction overrun fetch
Branch destination instruction
Branch destination
Next-
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