HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 335
HD6417020SVX12I
Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12I
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
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Quantity:
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11.3.2
If TPC output is enabled, next data register (NDRA/NDRB) contents are transferred to the data
register (PBDR) and output when the selected compare-match occurs. Figure 11.3 shows the
timing of these operations. The example is of ordinary output upon compare match A with groups
2 and 3.
11.3.3
Settings for Ordinary TPC Output (figure 11.4):
1. Select GRA as the output compare register (output disable) with the timer I/O control register
2. Set the TPC output trigger cycle.
3. Select the counter clock with the TPSC2–TPSC0 bits of the timer control register (TCR).
4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR
5. Set the initial output value in the I/O port data register to be used by TPC.
6. Set the I/O port control register to be used by TPC as the TP pin function (11).
(TIOR).
Select the counter clear sources with the CCLR1 and CCLR0 bits.
can also be set using the DMAC.
TP15–TP8
Compare
match A
NDRB
PBDR
TCNT
signal
GRA
Output Timing
Examples of Use of Ordinary TPC Output
CK
Figure 11.3 Transfer and Output Timing for NDR Data
m
m
N
N
n
N + 1
n
n
RENESAS 317
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