HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 82
HD6417020SVX12I
Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12I
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number:
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5.1
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt
requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These
registers handle interrupt requests according to user-established priorities.
5.1.1
The interrupt controller has the following features:
•
•
•
5.1.2
Figure 5.1 is a block diagram of the interrupt controller.
16 settable priority levels: Five interrupt priority registers can set 16 levels of interrupt
priorities for IRQ and on-chip peripheral interrupt sources.
The INTC has an NMI input level T bit that indicates NMI pin status. By reading this bit with
the interrupt exception service routine, the pin status can be checked for use in a noise
canceller function.
The interrupt controller can notify external devices (via the IRQOUT pin) that an onchip
interrupt has been occured. In this way an external device can, for example, be informed if an
on-chip interrupt occurs while the chip is operating in a bus-released mode and the bus has
been requested.
Overview
Features
Block Diagram
Section 5 Interrupt Controller (INTC)
RENESAS 61
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