HD6417709SF133B Renesas Electronics America, HD6417709SF133B Datasheet - Page 298
HD6417709SF133B
Manufacturer Part Number
HD6417709SF133B
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of HD6417709SF133B
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2.05 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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10.2.7
The synchronous DRAM mode register (SDMR) is an 8-bit write-only register that is written to
via the synchronous DRAM address bus. It sets synchronous DRAM mode for areas 2 and 3.
SDMR must be set before accessing the synchronous DRAM.
Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If
the value to be set is X and the SDMR address is Y, the value X is written in the synchronous
DRAM mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the
synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is
connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value
shifted two bits right. With a 16-bit bus width, the value written is the X value shifted one bit
right. For example, with a 32-bit bus width, when H'0230 is written to the SDMR register of area
2, random data is written to the address H'FFFFD000 (address Y) + H'08C0 (value X), or
H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. The range for value X is
H'0000 to H'0FFC. When H'0230 is written to the SDMR register of area 3, random data is written
to the address H'FFFFE000 (address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230
is written to the SDMR register. The range for value X is H'0000 to H'0FFC.
Note: * Depending on the type of synchronous DRAM.
Rev. 5.00, 09/03, page 252 of 760
Initial value:
Initial value:
Synchronous DRAM Mode Register (SDMR)
R/W:
R/W:
Bit:
Bit:
31
—
—
—
—
W
7
SDMR address
......................
......................
—
—
W
6
—
—
W
5
12
—
—
—
—
W
4
W *
11
—
—
—
—
W
3
W *
10
—
—
—
—
W
2
—
—
W
—
—
—
9
1
—
—
W
—
—
—
8
0
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