HD64F2636F20J Renesas Electronics America, HD64F2636F20J Datasheet - Page 31

IC H8S MCU FLASH 128K 128QFP

HD64F2636F20J

Manufacturer Part Number
HD64F2636F20J
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2636F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Section 1 CPU
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction
on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
(4) Multiply-Accumulate Register (MAC)
The MAC register is supported only by the H8S/2600 CPU. This 64-bit register stores the results
of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and
MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension.
1.4.4
Initial Register Values
Reset exception handling loads the CPU’s program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack pointer should therefore be initialized by an MOV.L instruction executed immediately
after a reset.
Rev. 4.00 Feb 24, 2006 page 15 of 322
REJ09B0139-0400

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