MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 105
MC68HC908LB8CPE
Manufacturer Part Number
MC68HC908LB8CPE
Description
IC MCU 8K FLASH 8MHZ 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908LB8CDWE.pdf
(234 pages)
Specifications of MC68HC908LB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVR, POR, PWM
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LB8CPE
Manufacturer:
IR
Quantity:
10
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10.8 HRP Registers
The following registers control and monitor operation of the HRP:
10.8.1 HRP Control Register
The HRPCTRL register does the following:
SHTLVL — SHTDWN Pin Level
HRPOE — HRP Output Enable
SHTIF — SHTDWN Interrupt Flag
SHTIE — SHTDWN Interrupt Enable
SHTEN — Shutdown Pin Enable
Freescale Semiconductor
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This read-only bit contains the current logic level of the SHTDWN pin. Reset clears the SHTLVL bit.
This read/write bit enables/disables the TOP and BOT output pins.
This read/write bit is set when a falling edge or a low level is detected on the SHTDWN pin. Reset
clears the SHTIF bit. Writing 0 to SHTIF clears the bit.
This read/write bit enables HRP CPU interrupt service requests for the SHTDWN pin. Reset clears the
SHTIE bit.
1 = Pins PTB0/TOP and PTB1/BOT function as TOP and BOT outputs from the HRP module. The
0 = Pins PTB0/TOP and PTB1/BOT function as PTB0 and PTB1 general-purpose I/O pins. The
1 = SHTDWN pin interrupt pending
0 = No SHTDWN pin interrupt pending
1 = SHTDWN CPU interrupt requests enabled
0 = SHTDWN CPU interrupt requests disabled
HRP control register (HRPCTRL)
HRP duty cycle registers (HRPDCH: HRPDCL)
HRP period registers (HRPPERH:HRPPERL)
HRP deadtime register (HRPDT)
HRP timebase registers (HRPTBH:HRPTBL)
Enables the HRP
Controls the operating mode of the HRP
Enables the SHTDWN, TOP, and BOT pins
Enables interrupt functionality for the SHTDWN pin
contents of the port B data and data direction registers do not affect these pins.
state of these pins is controlled by the port B data and data direction registers.
Address: $0051
Reset:
Read:
Write:
Bit 7
Figure 10-10. HRP Control Register (HRPCTRL)
= Unimplemented
SHTLVL
6
0
MC68HC908LB8 Data Sheet, Rev. 1
HRPOE
5
0
SHTIF
4
0
SHTIE
3
0
SHTEN
2
0
MODE
HRP-
1
0
HRPEN
Bit 0
0
HRP Registers
105
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