MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 199
MC68HC908LB8CPE
Manufacturer Part Number
MC68HC908LB8CPE
Description
IC MCU 8K FLASH 8MHZ 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908LB8CDWE.pdf
(234 pages)
Specifications of MC68HC908LB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVR, POR, PWM
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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Manufacturer
Quantity
Price
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Part Number:
MC68HC908LB8CPE
Manufacturer:
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CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
ELSxB and ELSxA — Edge/Level Select Bits
Freescale Semiconductor
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1
channel 0 and TIM2 channel 0 status and control registers.
Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose
I/O.
Reset clears the MSxB bit.
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output
compare/PWM operation. See
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See
Reset clears the MSxA bit.
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is
available as a general-purpose I/O pin.
the ELSxB and ELSxA bits.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM status and control register (TSC).
Before enabling a TIM channel register for input capture operation, make
sure that the PTD/TCHx pin is stable for at least two bus clocks.
Table
MC68HC908LB8 Data Sheet, Rev. 1
18-2.
Table 18-2
NOTE
NOTE
shows how ELSxB and ELSxA work. Reset clears
Table
I/O Registers
18-2.
199
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