MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 621
MPC564CVR40
Manufacturer Part Number
MPC564CVR40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CVR40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CVR40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Standard SCI features are listed below, followed by a list of additional features offered.
Standard SCI two-wire system features:
Standard SCI receiver features:
Standard SCI transmitter features:
QSMCM-additional SCI features:
QSMCM-enhanced SCI features:
15.2.1
The QSMCM module has an identical function to the MPC555. The MUXing of the pins is controlled by
the QPAPCS3 bit in the QSMCM pin assignment register (PQSPAR).
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Programmable Transfer Delay — from 0.6 µs to 0.3 µs (at 28 MHz)
Programmable Queue Pointer
Continuous Transfer Mode — up to 256 bits
Optional on-chip expanded QSPI chip selects
Standard nonreturn-to-zero (NRZ) mark/space format
Advanced error detection mechanism (detects noise duration up to 1/16 of a bit-time)
Full-duplex operation
Software selectable word length (8- or 9-bit words)
Separate transmitter and receiver enable bits
May be interrupt driven
Four separate interrupt enable bits
Two independent operating SCI modules
Receiver wakeup function (idle or address mark bit)
Idle-line detect
Framing, noise, and overrun error detect
Receive data register full flag
Transmit data register empty flag
Transmit complete flag
Send break
13-bit programmable baud-rate modulus counter
Even/odd parity generation and detection
Two idle-line detect modes
Receiver active flag
16 register receive buffer on one SCI
16 register transmit buffer on one SCI
MPC561/MPC563 QSMCM Details
MPC561/MPC563 Reference Manual, Rev. 1.2
Queued Serial Multi-Channel Module
15-3
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