EG80C196EA Intel, EG80C196EA Datasheet - Page 18
EG80C196EA
Manufacturer Part Number
EG80C196EA
Description
IC MPU 16-BIT 5V 40MHZ 160-QFP
Manufacturer
Intel
Series
80Cr
Datasheet
1.S80C196EA.pdf
(32 pages)
Specifications of EG80C196EA
Core Processor
MCS 96
Core Size
16-Bit
Speed
40MHz
Connectivity
SIO
Peripherals
PWM, WDT
Number Of I /o
83
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Other names
864391
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EG80C196EA
Manufacturer:
INTL
Quantity:
3 767
80C196EA - Commercial
14
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2)
Table 8. AC Timing Symbol Definitions
T
T
T
T
T
T
T
T
T
T
T
NOTES:
A
B
C
D
† Address bus (demultiplexed mode) or address/data bus (multiplexed mode)
1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be
2. If wait states are used, add 2t
3. Assuming back-to-back bus cycles.
4. When forcing wait states using the BUSCON register, add 2t
5. Exceeding the maximum specification causes additional wait states.
6. 8-bit bus only.
7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait
8. Device is static by design but has been tested only down to 20 MHz.
9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Symbol
WHQX
WHLH
WHBX
WHAX
RHBX
RHAX
WHSH
RHSH
AVYV
CLYX
YLYH
†
applied with an external clock source.
state is required.
Address
BHE#
CLKOUT
Input Data
Data Hold after WR# High
WR# High to ALE High
BHE#, INST Hold after WR# High
AD15:8, CS x # Hold after WR# High
BHE#, INST Hold after RD# High
AD15:8, CS x # Hold after RD# High
A20:0, CS x # Hold after WR# High
A20:0, CS x # Hold after RD# High
AD15:0 Valid to READY Setup
READY Hold after CLKOUT Low
Non-READY Time
L
Q
R
S
ALE
Output Data
RD#
CS x #
n , where n = number of wait states.
Parameter
Signals
W
X
Y
WR#, WRH#, WRL#
XTAL1
READY
n.
t – 20
t – 15
t – 4
t – 4
t – 5
t – 5
Min
No Upper Limit
0
0
0
Preliminary Datasheet
H
L
V
X
Z
2t – 40
2t – 40
t + 10
Max
High
Low
Valid
No Longer Valid
Floating
Conditions
ns (5, 7, 9)
ns (6)
ns (6)
ns (4)
Units
ns
ns
ns
ns
ns
ns
ns