MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 20

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

2.10.4 Port D
2-8
output port suitable for wired-OR operation. In wired-OR mode (a port C bit is at logic
level zero), it is actively driven low by the N-channel driver. When a port C bit is at logic
level one, the associated pin has high impedance, as neither the N- nor the P-channel
devices are active. It is customary to have an external pullup resistor on lines that are
driven by open-drain devices. Port C can only be configured for wired-OR operation
when the MCU is in single-chip mode. Refer to SECTION 6 PARALLEL I/O for addi-
tional information about port C functions.
Port D, an 8-bit, general-purpose I/O port has a data register (PORTD) and a data di-
rection register (DDRD). The eight port D bits (D[7:0]) can be used for general-purpose
I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)
subsystems, or for bus data direction control.
Port D can be read at any time and inputs return the sensed levels at the pin; whereas,
the outputs return the input level of the port D pin drivers. If PORTD is written, the data
is stored in an internal latch, and can be driven only if port D is configured for general-
purpose output. This port shares functions with the on-chip SCI and SPI subsystems,
while bits 6 and 7 control the direction of data flow on the bus in expanded and special
test modes.
Refer to SECTION 6 PARALLEL I/O.
Freescale Semiconductor, Inc.
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PIN DESCRIPTIONS
TECHNICAL DATA