MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 33

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

TECHNICAL DATA
SUBD (opr)
Mnemonic
SBCA (opr)
SBCB (opr)
STAA (opr)
STAB (opr)
SUBA (opr)
SUBB (opr)
STX (opr)
STD (opr)
STS (opr)
STY (opr)
TST (opr)
STOP
TEST
TSTA
TSTB
SEC
SEV
SWI
TAB
TAP
TBA
TPA
SEI
Transfer A to B
Transfer B to A
Test A for Zero
Test B for Zero
TEST (Only in
Subtract with
Subtract with
Memory from
Memory from
Memory from
Transfer A to
Register to A
Carry from A
Carry from B
Set Overflow
Stop Internal
Test for Zero
Set Interrupt
Accumulator
Accumulator
Accumulator
CC Register
Test Modes)
Transfer CC
Store Stack
Store Index
Store Index
Operation
Register X
Register Y
Set Carry
Software
or Minus
or Minus
or Minus
Subtract
Subtract
Subtract
Interrupt
Pointer
Clocks
Mask
Store
Store
Store
Flag
A
B
D
A
B
D
Address Bus Counts
A
D – M : M + 1
SP
See Figure 3–2
A – M – C
B – M – C
IX
IY
Description
A – M
B – M
A
CCR
M, B
A
B
A
B
1
1
M – 0
1
A – 0
B – 0
Freescale Semiconductor, Inc.
M : M + 1
M : M + 1
Table 3-2 Instruction Set (Sheet 6 of 7)
M : M + 1
—
CCR
C
M
M
For More Information On This Product,
V
B
A
I
A
M + 1
A
B
A
B
D
CENTRAL PROCESSING UNIT
A
A
A
A
A
B
B
B
B
B
A
A
A
A
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
B
Addressing
Go to: www.freescale.com
Mode
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
INH
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
INH
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
INH
INH
INH
INH
INH
INH
EXT
IND,X
IND,Y
INH
INH
18
18
18
18
18
18
CD
18
18
1A
18
18
18
18
18
Opcode
82
92
A2
A2
C2
D2
E2
E2
0D
0F
0B
97
B7
D7
F7
DD
FD
CF
9F
BF
DF
FF
DF
FF
EF
EF
80
90
A0
A0
C0
D0
E0
E0
83
93
A3
A3
3F
16
06
17
00
07
7D
6D
6D
4D
5D
B2
F2
A7
A7
E7
E7
ED
ED
AF
AF
EF
EF
B0
F0
B3
Instruction
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
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ff
ff
dd
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ff
ff
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dd
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ff
dd
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ff
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
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ff
ff
hh ll
ff
ff
Operand Cycles
—
—
—
—
—
—
—
—
—
—
—
—
14
2
3
4
4
5
2
3
4
4
5
2
2
2
3
4
4
5
3
4
4
5
4
5
5
6
2
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
2
2
2
2
6
6
7
2
2
*
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H
Condition Codes
—
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1
1
I
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N
—
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Z
—
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V
1
0
0
0
0
0
0
0
0
0
0
0
3-13
—
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—
—
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C
1
0
0
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