MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 44

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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OPTION — System Configuration Options
4.2.2.3 OPTION Register
Bits [7:6] and 2 — Not implemented
IRQE — IRQ Select Edge Sensitive only
DLY — Enable Oscillator Startup Delay
CME — Clock Monitor Enable
CR[1:0] — COP Timer Rate Select Bits
4-10
RESET:
The 8-bit special-purpose OPTION register sets internal system configuration options
during initialization. The time protected control bits, IRQE, DLY, and CR[1:0] can be
written to only once after a reset and then they become read-only. This minimizes the
possibility of any accidental changes to the system configuration.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes
Always read zero
Refer to SECTION 5 RESETS AND INTERRUPTS.
The internal E clock is first divided by 2
These control bits determine a scaling factor for the watchdog timer. Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
0 = IRQ is configured for level sensitive operation
1 = IRQ is configured for edge sensitive only operation
0 = The oscillator startup delay coming out of STOP is bypassed and the MCU re-
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
sumes processing within about four bus cycles.
up from the STOP power-saving mode. This delay allows the crystal oscillator
to stabilize.
Bit 7
0
0
Freescale Semiconductor, Inc.
6
0
0
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
IRQE*
Go to: www.freescale.com
5
0
DLY*
15
4
1
before it enters the COP watchdog system.
CME
3
0
2
0
0
CR1*
TECHNICAL DATA
1
0
$0039
CR0*
Bit 0
0

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