MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 65

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E0CFNE3

Manufacturer Part Number
MC68HC11E0CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E0CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Digital Ic Case Style
LCC
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E0CFNE3
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FREESCALE
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6 249
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MC68HC11E0CFNE3
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PORTD — Port D Data
DDRD — Data Direction Register for Port D
PACTL — Pulse Accumulator Control
DDD[7:0] — Data Direction for Port D
DDRA7 — Data Direction Control for Port A Bit 7
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
DDRA3 — Data Direction for Port A Bit 3
TECHNICAL DATA
Alt. Func.:
RESET:
RESET:
RESET:
When port D is a general-purpose I/O port, the DDRD register controls the direction of
the I/O pins as follows:
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W outputs.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave
select (SS) input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master
mode, DDD5 affects port D bit 5 as follows:
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be
inputs, then they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI
expects port D bits 2, 3, and 4 to be outputs, they are outputs only if DDRD bits 2, 3,
and 4 are set.
Refer to SECTION 9 TIMING SYSTEM.
Refer to SECTION 9 TIMING SYSTEM.
Refer to SECTION 9 TIMING SYSTEM.
Refer to SECTION 9 TIMING SYSTEM.
Overridden if an output compare function is configured to control the PA3 pin.
0 = Configures the corresponding port D pin for input
1 = Configures the corresponding port D pin for output
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
0 = Input only
1 = Output
DDRA7
DDD7
Bit 7
PD7
R/W
Bit 7
Bit 7
0
0
0
DDD6
PAEN
PD6
AS
Freescale Semiconductor, Inc.
6
0
6
0
6
0
For More Information On This Product,
PAMOD
DDD5
PD5
Go to: www.freescale.com
5
0
5
0
5
0
PARALLEL I/O
PEDGE
DDD4
SCK
PD4
4
0
4
0
4
0
DDRA3
DDD3
MOSI
PD3
3
0
3
0
3
0
DDD2
MISO
I4/O5
PD2
2
0
2
0
2
0
DDD1
RTR1
PD1
TxD
1
0
1
0
1
0
$0008
$0009
$0026
DDD0
RTR0
Bit 0
Bit 0
Bit 0
PD0
RxD
0
0
0
6-3

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