MC68HC11E0CFNE3 Freescale Semiconductor, MC68HC11E0CFNE3 Datasheet - Page 95

• Manufacturer Part Number: MC68HC11E0CFNE3
• Description: IC MCU 8BIT 3MHZ 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11E0CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Type: ROMless
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Controller Family/series: 68HC11
• No. Of I/o's: 38
• Ram Memory Size: 512Byte
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Digital Ic Case Style: LCC
• Rohs Compliant: Yes
• Processor Series: HC11E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

OC1M — Output Compare 1 Mask
OC1D — Output Compare 1 Data
TCNT — Timer Counter
OC1M7–OC1M3 — Output Compare Masks
Bits [2:0] — Not implemented; always read zero
9.3.4 Output Compare 1 Data Register
Bits [2:0] — Not implemented; always read zero
9.3.5 Timer Counter Register
TCNT resets to $0000.
9.3.6 Timer Control 1 Register
TECHNICAL DATA
RESET:
RESET:
$000E
$000F
Set bit(s) to enable OC1 to control corresponding pin(s) of port A.
Use this register with OC1 to specify the data that is to be stored on the affected pin
of port A after a successful OC1 compare. When a successful OC1 compare occurs,
a data bit in OC1D is stored in the corresponding bit of port A for each bit that is set in
OC1M.
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares.
The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A
full counter read addresses the most significant byte (MSB) first. A read of this address
causes the least significant byte (LSB) to be latched into a buffer for the next CPU cy-
cle so that a double-byte read returns the full 16-bit state of the counter at the time of
the MSB read cycle.
In normal modes, TCNT is read-only.
The bits of this register specify the action taken as a result of a successful OCx com-
pare.
0 = OC1 is disabled
1 = OC1 is enabled to control the corresponding pin of port A
OC1M7
OC1D7
Bit 15
Bit 7
Bit 7
Bit 7
0
0
14
6
OC1M6
OC1D6
Freescale Semiconductor, Inc.
6
0
6
0
For More Information On This Product,
13
5
OC1M5
OC1D5
Go to: www.freescale.com
5
0
5
0
12
4
TIMING SYSTEM
OC1M4
OC1D4
11
3
4
0
4
0
10
2
OC1M3
OC1D3
3
0
3
0
9
1
2
0
0
2
0
0
Bit 8
Bit 0
$000E, $000F
1
0
0
1
0
0
TCNT (High)
TCNT (Low)
$000C
$000D
Bit 0
Bit 0
0
0
0
0
9-9