M306N5FCTFP Renesas Electronics America, M306N5FCTFP Datasheet - Page 269

• Manufacturer Part Number: M306N5FCTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N5FCTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.2 Interrupt Control
Chapter 5
The following explains how to enable/disable maskable interrupts and set acknowledge priority. The expla-
nation here does not apply to non-maskable interrupts.
Maskable interrupts are enabled and disabled by using the interrupt enable flag (I flag), interrupt priority
level select bit, and processor interrupt priority level (IPL). Whether there is any interrupt requested is
indicated by the interrupt request bit. The interrupt request bit and interrupt priority level select bit are
arranged in the interrupt control register provided for each specific interrupt. The interrupt enable flag (I
flag) and processor interrupt priority level (IPL) are arranged in the flag register (FLG).
For details about the memory allocation and the configuration of interrupt control registers, refer to the
M16C User's Manual.
Figure 5.2.1 Timing at which changes of I flag are reflected in interrupt handling
5.2.1 Interrupt Enable Flag (I Flag)
5.2.2 Interrupt Request Bit
When changed by REIT instruction
When changed by FCLR, FSET, POPC, or LDC instruction
The interrupt enable flag (I flag) is used to disable/enable maskable interrupts. When this flag is set (=
1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. This flag is
automatically cleared to 0 after a reset is cleared.
When the I flag is changed, the altered flag status is reflected in determining whether or not to accept an
interrupt request at the following timing:
This bit is set (= 1) when an interrupt request is generated. This bit remains set until the interrupt request
is acknowledged. The bit is cleared to 0 when the interrupt request is acknowledged.
This bit can be cleared to 0 (but cannot be set to 1) in software.
• If the flag is changed by an REIT instruction, the changed status takes effect beginning with that
• If the flag is changed by an FCLR, FSET, POPC, or LDC instruction, the changed status takes
REIT instruction.
effect beginning with the next instruction.
Interrupt request generated
Interrupt
Interrupt request generated
Previous
instruction
(If I flag is changed from 0 to 1 by REIT instruction)
Previous
instruction
(If I flag is changed from 0 to 1 by FSET instruction)
Determination whether or not to
accept interrupt request
FSET I
REIT
251
Interrupt sequence
Next instruction
Determination whether or not to
accept interrupt request
Interrupt sequence
Ti m e
Ti m e
5.2 Interrupt Control