DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 306
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2315VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 I/O Ports
8.9.2
Table 8.15 shows the port D register configuration.
Table 8.15 Port D Registers
Name
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
• Modes 4 to 6 *
• Mode 7 *
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 272 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
Setting PDDDR bits to 1 makes the corresponding port D pins output ports, while clearing the
bits to 0 makes the pins input ports.
Register Configuration
:
:
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
W
7
0
W
6
0
Abbreviation
PDDDR
PDDR
PDPCR
PORTD
W
5
0
W
4
0
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
W
2
0
W
1
0
Address *
H'FEBC
H'FF6C
H'FF5C
H'FF73
W
0
0
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