DF2315VTE25 Renesas Electronics America, DF2315VTE25 Datasheet - Page 547
DF2315VTE25
Manufacturer Part Number
DF2315VTE25
Description
MCU 3V 384K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2315VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2315VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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13.3.4
Table 13.3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 13.3 Smart Card Interface Register Settings
Register
SMR
BRR
SCR
TDR
SSR
RDR
SCMR
Notes: — : Unused bit.
SMR Settings: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in
GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1
if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the built-in baud rate generator, and bits BCP1
and BCP0 select the number of base clock cycles during transfer of one bit. For details, see section
13.3.5, Clock.
The BLK bit is cleared to 0 when using the normal smart card interface mode, and set to 1 when
using block transfer mode.
BRR Setting: BRR is used to set the bit rate. See section 13.3.5, Clock, for the method of
calculating the value to be set.
SCR Settings: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 12, Serial Communication Interface (SCI).
* The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.
Register Settings
Bit 7
GM
BRR7
TIE
TDR7
TDRE
RDR7
—
Bit 6
BLK
BRR6
RIE
TDR6
RDRF
RDR6
—
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
ERS
RDR4
—
Bit
Bit 3
BCP1
BRR3
0
TDR3
PER
RDR3
SDIR
Rev.7.00 Feb. 14, 2007 page 513 of 1108
Section 13 Smart Card Interface
Bit 2
BCP0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1 *
TDR1
0
RDR1
—
REJ09B0089-0700
BRR0
TDR0
RDR0
Bit 0
CKS0
CKE0
0
SMIF
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