M30626FJPGP#D3C Renesas Electronics America, M30626FJPGP#D3C Datasheet - Page 286

• Manufacturer Part Number: M30626FJPGP#D3C
• Description: MCU 3/5V 512K 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#D3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6
Figure 6.1.3. When executing an instruction to read from even addresses starting from an even address
Figure 6.1.4. When executing an instruction to read from odd addresses starting from an even address
Instructions
under execution
Address bus
Fetch code
Instruction
queue buffer
BCLK
Data bus (H)
Data bus (L)
RD
WR
RD
Instructions
under execution
Fetch code
Instruction
queue buffer
BCLK
Address bus
Data bus (H)
Data bus (L)
WR
DR : Indicates a data read.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
DR : Indicates a data read.
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
04
04
04
Jump address
64
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Jump address
FC064
04
04
04
64
04
04
04
JMP
FC05A
04
04
04
TEST_11
04
04
04
JMP
Low-order address from
which to read data
FC068
04
04
04
TEST_11
73
73
F1
Address from which to read data
F1
P
73
FC05E
Fetch
FC06A
73
73
F1
F1
73
01
40
F1
P
73
P
40
00
Fetch
Fetch
FC060
FC06C
73
F1
00
40
73F1
00
40
64
04
40
P
00
64
04
P
Fetch
FC062
73F1
04001
00
40
64
04
0040
64
04
Read from even
address
64
04
P
MOV.W
AA
DR
MOV.W
04000
0040
04002
64
04
64
04
AA
AA
DR
Content at address 4001
AA
DR
Fetch
High-order address from
which to read data
Fetch
64
04
04
04
64
04
04
04
Content at address 4001
Content at address 4000
04
04
P
Content at address 4002
04
04
P
64
04
04
04
64
FC064
04
04
04
268
FC06E
04
04
04
04
04
04
JMP
JMP
16
04
04
04
TEST_12
TEST_12
04
04
04
16
16
16
FC068
FC072
73
F1
73
F1
73
F1
P
F1
73
P
Content at jump address is
prefetched at the same time
the instruction queue buffer is
cleared.
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
FC06A
FC074
73
F1
00
40
73
F1
00
40
00
40
00
40
P
P
Calculation number of cycles
Sample program
Address
FC058
FC059
FC05A
FC05B
FC05C
FC05D
FC05E
FC05E
FC062
FC063
FC064
FC065
FC066
FC067
FC068
Sample program
Address
FC062
FC063
FC064
FC065
FC066
FC067
FC068
FC068
FC06C
FC06D
FC06E
FC06F
FC070
FC071
FC072
Code
64
04
04
04
04
04
73F10040
64
04
04
04
04
04
6.1 Instruction queue buffer
TEST_11:
TEST_12:
Code
64
04
04
04
04
04
73F10140
64
04
04
04
04
04
TEST_11:
TEST_12:
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
Instruction
JMP
NOP
NOP
NOP
NOP
NOP
MOV.W
JMP
NOP
NOP
NOP
NOP
NOP
TEST_11
TEST_12
04000h, R1
TEST_11
04001h, R1
TEST_12