M30626FJPGP#D3C Renesas Electronics America, M30626FJPGP#D3C Datasheet - Page 68

MCU 3/5V 512K 100-LQFP

M30626FJPGP#D3C

Manufacturer Part Number
M30626FJPGP#D3C
Description
MCU 3/5V 512K 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPGP#D3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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[ Operation ]
BNAND
[ Syntax ]
[ Function ]
[ Selectable src ]
[ Flag Change ]
[ Description Example ]
[ Related Instructions ]
Chapter 3
Change
bit,R0
bit,A0
base:8[A0]
base:16[A0]
C
Condition
BNAND
Flag
C
• This instruction logically ANDs the C flag and inverted src together and stores the result in the C flag.
C :
BNAND
BNAND
BNAND
BNAND
U
The flag is set when the operation resulted in 1; otherwise cleared.
______
src
bit,R1
bit,A1
base:8[A1]
base:16[A1]
bit,base:11[SB]
I
Functions
src
flag
4,Ram
16,Ram:16[SB]
[A0]
O
C
B
src
bit,R2
[A0]
bit,base:16[SB] bit,base:16
bit,base:8[SB] bit,base:8[FB]
S
BAND,BOR,BXOR,BNOR,BNXOR
Z
D
Logically AND inverted bits
bit,R3
[A1]
Bit Not AND carry flag
C
50
[ Instruction Code/Number of Cycles ]
BNAND
3.2
Page= 155
Functions

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