M30626FJPGP#D3C Renesas Electronics America, M30626FJPGP#D3C Datasheet - Page 80

MCU 3/5V 512K 100-LQFP

M30626FJPGP#D3C

Manufacturer Part Number
M30626FJPGP#D3C
Description
MCU 3/5V 512K 100-LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626FJPGP#D3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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CMP
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src/dest ]
[ Flag Change ]
[ Description Example ]
Chapter 3
*1 If you specify (.B) for the size specifier (.size), you cannot choose A0 or A1 for src and dest simulta-
Change
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
Conditions
CMP.size (:format) src,dest
dest
Flag
• Each flag bit of the flag register varies depending on the result of subtraction of src from dest .
• If dest is an A0 or A1 when the size specifier (.size) you selected is (.B), src is zero-expanded to
O :
S :
Z :
C :
CMP.B:S
CMP.W:G
CMP.W
CMP.B
CMP.B
neously.
perform operation in 16 bits. If src is an A0 or A1, operation is performed on the 8 low-order bits of A0
or A1.
*1
U
The flag is set when a signed operation resulted in exceeding +32767 (.W) or –32768 (.W), or
+127 (.B) or –128 (.B); otherwise cleared.
The flag is set when the operation resulted in MSB = 1; otherwise cleared.
The flag is set when the operation resulted in 0; otherwise cleared.
The flag is set when an unsigned operation resulted in any value equal to or greater than 0;
otherwise cleared.
src
R0H/R1
A1/A1
dsp:8[A1]
R3R1
I
Functions
#10,R0L
R0,A0
#–3,R0
#5,Ram:8[FB]
A0,R0L
O
*1
B
src
S
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
Z
D
C
R1H/R3
[A1]
dsp:8[FB] dsp:8[A0]
abs16
#IMM
G , Q , S (Can be specified)
B , W
(See the next page for src / dest classified by format.)
CoMPare
Compare
62
R0L/R0
A0/A0
dsp:16[A0] dsp:16[A1] dsp:16[SB] abs16
dsp:20[A0] dsp:20[A1] abs20
R2R0
; A0’s 8 low-order bits and R0L are compared.
*1
R0H/R1
A1/A1
dsp:8[A1]
R3R1
[ Instruction Code/Number of Cycles ]
*1
dest
R1L/R2
[A0]
dsp:8[SB]
A1A0
R1H/R3
[A1]
dsp:8[FB]
SP/SP
3.2 Functions
CMP
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