MC9S12XA512VAG Freescale Semiconductor, MC9S12XA512VAG Datasheet - Page 203
MC9S12XA512VAG
Manufacturer Part Number
MC9S12XA512VAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512VAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LQFP
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Operating Supply Voltage
0 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512VAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The programmer’s model of the XGATE RISC core is shown in
seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An additional
eighth register (R0) is tied to the value “$0000”. Register R1 has an additional functionality. It is preloaded
with the initial variable pointer of the channel’s service request vector (see
of the remaining general purpose registers is undefined.
The 16 bit program counter allows the addressing of a 64 kbyte address space.
The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and
the carry bit (C). The initial content of the condition code register is undefined.
6.4.3
The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks
within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed
information.
The XGATE vector block assigns a start address and a variable pointer to each XGATE channel. Its
position in the XGATE memory map can be adjusted through the XGVBR register (see
“XGATE Vector Base Address Register
Each vector consists of two 16 bit words. The first contains the start address of the service routine. This
value will be loaded into the program counter before a service routine is executed. The second word is a
pointer to the service routine’s variable space. This value will be loaded into register R1 before a service
routine is executed.
Freescale Semiconductor
XGVBR
+$0000
+$0024
+$0028
+$002C
+$0030
+$01E0
Memory Map
Channel $09 Initial Program Counter
Channel $09 Initial Variable Pointer
Channel $0A Initial Program Counter
Channel $0A Initial Variable Pointer
Channel $0B Initial Program Counter
Channel $0B Initial Variable Pointer
Channel $0C Initial Program Counter
Channel $0C Initial Variable Pointer
Channel $78 Initial Program Counter
Channel $78 Initial Variable Pointer
unused
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 6-20. XGATE Vector Block
(XGVBR)”).
Figure 6-20
Figure
shows the layout of the vector block.
6-19. The processor offers a set of
Variables
Figure
Variables
Code
Code
Chapter 6 XGATE (S12XGATEV2)
6-20). The initial content
Section 6.3.1.3,
203
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