R5F21226JFP#U0 Renesas Electronics America, R5F21226JFP#U0 Datasheet - Page 198
R5F21226JFP#U0
Manufacturer Part Number
R5F21226JFP#U0
Description
IC R8C/22 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/22r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21226JFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21226JFP#U0R5F21226JFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
R5F21226JFP#U0R5F21226JFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.30
Perform the following for the timer mode (input capture and output compare functions).
When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register
When using the TRDGRDi register as the buffer register of the TRDGRBi register
Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using
registers TRDGRCi and TRDGRDi as the buffer register in the input capture function.
When using the TRDGRCi and TRDGRDi registers for the buffer register in output compare function, reset
synchronous PWM mode, complementary PWM mode and PWM3 mode, the IMFC and IMFD bits in the
TRDSRi register are set to 1 by the compare match with the TRDi register.
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same as the IOA2 bit in the TRDIORAi register.
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
i = 0 or 1
The above applies to the following conditions:
• BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of
• IOA2 to IOA0 bits in the TRDIORAi register are set to 001b (“L” output by the compare match).
the TRDGRAi register.)
Buffer Operation in Output Compare Function
TRDGRCi register
TRDGRAi register
TRDIOAi output
TRDi register
Page 176 of 501
(buffer)
TRDGRCi
register
(buffer)
m-1
Compare match signal
m
TRDGRAi
register
m
n
Comparator
Transfer
n
m+1
TRDi
14. Timers
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