R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 193
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
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Part Number:
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6.4.12
Format
BT/S
Description
Reads the T bit and conditionally branches. If T = 1, BT/S branches after the following instruction
executes. If T = 0, BT/S executes the next instruction. The branch destination is an address
specified by PC + displacement. However, in this case it is used for address calculation. The PC is
the address 4 bytes after this instruction. The 8-bit displacement is sign-extended and doubled.
Consequently, the relative interval from the branch destination is –256 to +254 bytes. If the
displacement is too short to reach the branch destination, use BT/S with the BRA instruction or the
like.
Note
Since this is a delay branch instruction, the instruction immediately following is executed before
the branch. No interrupts and address errors are accepted between this instruction and the next
instruction. When the immediately following instruction is a branch instruction, it is recognized as
an illegal slot instruction. When branching, requires two cycles; when not branching, one cycle.
label
BT/S
Conditional Branch with Delay
When T = 1, disp × 2 + PC → PC;
Abstract
When T = 0, nop
Branch if True with delay Slot
Code
10001101dddddddd
Rev. 3.00 Jul 08, 2005 page 177 of 484
Section 6 Instruction Descriptions
Branch Instruction
Delayed Branch Instruction
REJ09B0051-0300
Cycle
2/1
T Bit
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