R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 201

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.16
Format
DIV0S Rm,Rn
Description
DIV0S is an initialization instruction for signed division. It finds the quotient by repeatedly
dividing in combination with the DIV1 or another instruction that divides for each bit after this
instruction. See the description given with DIV1 for more information.
Operation
Example: See DIV1.
DIV0S(long m,long n)
{
}
if ((R[n]&0x80000000)==0) Q=0;
else Q=1;
if ((R[m]&0x80000000)==0) M=0;
else M=1;
T=!(M==Q);
PC+=2;
DIV0S
Initialization for
Signed Division
Abstract
MSB of Rn → Q, MSB of Rm → M,
M^Q → T
DIVide (step 0) as Signed
/* DIV0S Rm,Rn */
Code
0010nnnnmmmm0111
Rev. 3.00 Jul 08, 2005 page 185 of 484
Section 6 Instruction Descriptions
Arithmetic Instruction
Cycle
1
REJ09B0051-0300
T Bit
Calculation result