R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 271
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.4.56
Format
SHLR2
SHLR8
SHLR16 Rn
Description
Logically shifts the contents of general register Rn to the right by 2, 8, or 16 bits, and stores the
result in Rn. Bits that are shifted out of the operand are not stored (figure 6.12).
SHLRn
n-Bit Right
Logical Shift
Rn
Rn
Rn>>2 → Rn
Rn>>8 → Rn
Rn>>16 → Rn
Abstract
SHLR2
SHLR8
SHLR16
Figure 6.12 Shift Logical Right n Bits
n bits SHift Logical Right
0
0
0
MSB
MSB
MSB
Code
0100nnnn00001001
0100nnnn00011001
0100nnnn00101001
Rev. 3.00 Jul 08, 2005 page 255 of 484
Section 6 Instruction Descriptions
Shift Instruction
LSB
LSB
LSB
Cycle
1
1
1
REJ09B0051-0300
T Bit
—
—
—
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