SAK-TC1766-192F80HL BD Infineon Technologies, SAK-TC1766-192F80HL BD Datasheet - Page 43

• Manufacturer Part Number: SAK-TC1766-192F80HL BD
• Description: IC MCU 32BIT FLASH PG-LQFP-176
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1766-192F80HL BD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1.5MB (1.5M x 8)
• Program Memory Type: FLASH
• Ram Size: 108K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 2x10b; A/D 32x8b,10b,12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 108.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.5 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: KT1766192F80HLBDXT; SAK-TC1766-192F80HLBDINTR

Preliminary
3.10
The MSC interface provides a serial communication link typically used to connect power
switches or other peripheral devices. The serial communication link includes a fast
synchronous downstream channel and a slow asynchronous upstream channel.
Figure 3-6
Figure 3-6
The downstream and upstream channels of the MSC module communicate with the
external world via nine I/O lines. Eight output lines are required for the serial
communication of the downstream channel (clock, data, and enable signals). One out of
eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The
source of the serial data to be transmitted by the downstream channel can be MSC
register contents or data that is provided at the ALTINL/ALTINH input lines. These input
lines are typically connected to other on-chip peripheral units (for example with a timer
unit like the GPTA). An emergency stop input signal makes it possible to set bits of the
serial data stream to dedicated values in emergency cases.
Data Sheet
SR15 (from CAN)
ALTINL[15:0]
(from GPTA)
ALTINH[15:0]
EMGSTOPMSC
(from SCU)
Decoder
Interrupt
Address
Control
Control
To DMA
Clock
Micro Second Bus Interfaces (MSC0)
shows a global view of the MSC interface signals.
Block Diagram of the MSC Interfaces
f
f
MSC0
CLC0
SR[1:0]
SR[3:2]
16
16
1) SDI[7:1] are connected to high level
(Kernel)
Module
MSC0
39
FCLP
FCLN
SOP
SON
EN0
EN1
SDI[0]
1)
Control
Port 2
Functional Description
A2
A2
A2
A2
A1
C
C
C
C
FCLP0A
FCLN0
SOP0A
SON0
P2.11 / FCLP0B
P2.12 / SOP0B
P2.8 / EN00
P2.9 / EN01
P2.13 / SDI0
V1.0, 2008-04
MCA06255
TC1766