LF441CN National Semiconductor, LF441CN Datasheet - Page 7

• Manufacturer Part Number: LF441CN
• Description: IC LOW PWR JFET OP AMP 8-DIP
• Manufacturer: National Semiconductor
• Series: BI-FET II™r

Specifications of LF441CN

• Amplifier Type: J-FET
• Number Of Circuits: 1
• Slew Rate: 1 V/µs
• Gain Bandwidth Product: 1MHz
• Current - Input Bias: 10pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 150µA
• Voltage - Supply, Single/dual (±): ±5 V ~ 15 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Current - Output / Channel: -
• -3db Bandwidth: -
• Other names: *LF441CN; LF441

Application Hints
This device is a low power op amp with an internally
trimmed input offset voltage and JFET input devices
(BI-FET II) These JFETs have large reverse breakdown
voltages from gate to source and drain eliminating the need
for clamps across the inputs Therefore large differential
input voltages can easily be accommodated without a large
increase in input current The maximum differential input
voltage is independent of the supply voltages However nei-
ther of the input voltages should be allowed to exceed the
negative supply as this will cause large currents to flow
which can result in a destroyed unit
Exceeding the negative common-mode limit on either input
will force the output to a high state potentially causing a
reversal of phase to the output Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode
Exceeding the positive common-mode limit on a single input
will not change the phase of the output however if both
inputs exceed the limit the output of the amplifier will be
forced to a high state
The amplifier will operate with a common-mode input volt-
age equal to the positive supply however the gain band-
width and slew rate may be decreased in this condition
When the negative common-mode voltage swings to within
3V of the negative supply an increase in input offset voltage
may occur
The amplifier is biased to allow normal circuit operation with
power supplies of
may degrade the common-mode rejection and restrict the
output voltage swing
Detailed Schematic
g
3V Supply voltages less than these
7
The amplifier will drive a 10 k
over the full temperature range
Precautions should be taken to ensure that the power sup-
ply for the integrated circuit never becomes reversed in po-
larity or that the unit is not inadvertently installed backwards
in a socket as an unlimited current surge through the result-
ing forward diode within the IC could cause fusing of the
internal conductors and result in a destroyed unit
As with most amplifiers care should be taken with lead
dress component placement and supply decoupling in or-
der to ensure stability For example resistors from the out-
put to an input should be placed with the body close to the
input to minimize ‘‘pick-up’’ and maximize the frequency of
the feedback pole by minimizing the capacitance from the
input to ground
A feedback pole is created when the feedback around any
amplifier is resistive The parallel resistance and capaci-
tance from the input of the device (usually the inverting input
to AC ground) set the frequency of this pole In many in-
stances the frequency of this pole is much greater than the
expected 3 dB frequency of the closed loop gain and con-
sequently there is negligible effect on stability margin How-
ever if the feedback pole is less than approximately 6 times
the expected 3 dB frequency a lead capacitor should be
placed from the output to the input of the op amp The value
of the added capacitor should be such that the RC time
constant of this capacitor and the resistance it parallels is
greater than or equal to the original feedback pole time con-
stant
TL H 9297 – 13
load resistance to
g
10V