LP3470M5X-3.65/NOPB National Semiconductor, LP3470M5X-3.65/NOPB Datasheet - Page 6
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LP3470M5X-3.65/NOPB
Manufacturer Part Number
LP3470M5X-3.65/NOPB
Description
IC RESET CIRCUIT 3.65V SOT23-5
Manufacturer
National Semiconductor
Type
Simple Reset/Power-On Resetr
Datasheet
1.LP3470IM5X-2.63NOPB.pdf
(10 pages)
Specifications of LP3470M5X-3.65/NOPB
Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
1 ms Minimum
Voltage - Threshold
3.65V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
SOT-23-5, SC-74A, SOT-25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LP3470M5X-3.65
www.national.com
Application Information
RESET TIMEOUT PERIOD
The Reset Timeout Period (t
external capacitor (C
Ceramic chip capacitor rated at or above 10V is sufficient. The
Reset Timeout Period (t
lowing formula:
For example a C
delay due to t
should be left floating.
RESET OUTPUT
In applications like microprocessor (µP) systems, errors might
occur in system operation during power-up, power-down, or
brownout conditions. It is imperative to monitor the power
supply voltage in order to prevent these errors from occurring.
The LP3470 asserts a reset signal whenever the V
voltage is below a threshold (V
teed to be a logic low for V
reset threshold, the reset is kept asserted for a time period
(t
terval Reset goes to logic high. If a brownout condition occurs
(monitored voltage falls below the reset threshold minus a
small hysteresis), Reset goes low. When V
Timing Diagram
RP
) programmed by an external capacitor (C
RP
is needed in a certain application, the pin SRT
1
t
RP
of 100 nF will achieve a t
(ms) = 2000 x C
1
) connected to pin SRT of LP3470. A
RP
) can be calculated using the fol-
CC
RP
> 0.5V. Once V
RTH
) is programmable using an
) voltage. Reset is guaran-
1
(µF).
RP
CC
of 200 ms. If no
CC
1
); after this in-
returns above
exceeds the
CC
supply
6
the reset threshold, Reset remains low for a time period t
before going to logic high.
PULL-UP RESISTOR SELECTION
The LP3470's Reset output structure is a simple open-drain
N-channel MOSFET switch. A pull-up resistor (R
connected to V
R
output MOSFET (Q
than 680Ω guarantees this. R
to ensure a logic high while supplying all the leakage current
through the Reset pin. A resistor value of less than 68kΩ sat-
isfies this condition. A typical pull-up resistor value of 20 kΩ
is sufficient in most applications.
NEGATIVE-GOING V
The LP3470 is relatively immune to short duration negative-
going V
acteristics show the Maximum Transient Duration vs. Nega-
tive Transient Amplitude (graph titled Transient Rejection), for
which reset pulses are not generated. This graph shows the
maximum pulse width a negative-going V
typically have without causing a reset pulse to be issued. As
the transient amplitude increases (i.e. goes farther below the
reset threshold), the maximum allowable pulse width de-
creases. A 0.1 µF bypass capacitor mounted close to V
provides additional transient immunity.
1
should be large enough to limit the current through the
CC
transients (glitches). The Typical Operating Char-
CC
.
1
) below 10 mA. A resistor value of more
CC
TRANSIENTS
1
should also be small enough
10001604
CC
transient may
1
) should be
CC
RP