ISL88706IB844Z Intersil, ISL88706IB844Z Datasheet - Page 4
Manufacturer Part Number
IC SUPERVISOR 4.38V 8-SOIC
Simple Reset/Power-On Resetr
Specifications of ISL88706IB844Z
Number Of Voltages Monitored
Open Drain or Open Collector
140 ms Minimum
Voltage - Threshold
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
WDO Watchdog Output. This output is pulled low when the nominal 1.6s internal Watchdog Timer expires
Manual Reset Input. A reset signal is generated when this input is pulled low. The MR input is an
active low debounced input to which a user can connect a push-button to add manual reset capability
or drive with a signal. The MR pin has an internal 20kΩ pull-up.
Power Supply Terminal. The voltage at this pin is compared against an internal factory-programmed
voltage trip point, V
the power supply has stabilized. Thereafter, reset is again asserted whenever V
The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief
power-supply transients. The voltage threshold V
Power-Fail Input This is an auxiliary monitored voltage input with a 1.25V threshold that causes PFO
state to follow the PFI input state.
Power-Fail Output. This output goes high if the voltage on PFI is greater than 1.25V, otherwise PFO
Adjustable POR Time-out Delay Input. Connecting an external capacitor from C
allows the user to increase the Power-On Reset time-out (t
Watchdog Input. The Watchdog Input takes an input from a microprocessor and ensures that it
periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out, then
reset is asserted and WDO is pulled low. The internal Watchdog Timer is cleared whenever the WDI
sees a rising or falling edge or the device is manually reset. Floating WDI or connecting WDI to a
high-impedance three-state buffer disables the watchdog feature.
Active-Low Reset Output. The RST output is an active low output with an internal PMOS pull-up
that is pulled low to GND when reset is asserted. Reset is asserted whenever:
1. The device is first powered up
3. MR is asserted.
The reset output continues to be asserted for typically 200ms after V
threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless WDO
is connected to MR.
Active-High Reset Output. The RST pin functions identically to its complementary RST output but
is an active high push-pull output. RST is set high to V
Descriptions” on page 4 for more details on conditions that cause a reset.
and periodically resets until the watchdog is cleared. WDO also goes low during low V
not have a minimum pulse width. As soon as V
with no delay.
falls below its minimum voltage sense level or
is below the reset threshold, WDO stays low. However, unlike RESET, WDO does
. A reset is first asserted when the device is initially powered up to ensure that
rises above the reset threshold, WDO goes high
is specified in the part number suffix.
when reset is asserted. See the RST in “Pin
) from the nominal 200ms.
rises above the reset
falls below V
January 12, 2009