ISL88706IB844Z Intersil, ISL88706IB844Z Datasheet - Page 7

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ISL88706IB844Z

Manufacturer Part Number
ISL88706IB844Z
Description
IC SUPERVISOR 4.38V 8-SOIC
Manufacturer
Intersil
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of ISL88706IB844Z

Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
140 ms Minimum
Voltage - Threshold
4.38V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
ISL88706IB844Z
Manufacturer:
Intersil
Quantity:
3 000
Price:
Low Voltage Monitoring
These devices monitor both the voltage level of V
auxiliary voltage on PFI.
When IC is initially biased reset is asserted until the V
voltage is greater than the specific IC fixed-voltage trip point
for the t
V
again asserted, i.e. RST is high and RST is low (see
Figure 1).
Power Failure Monitor
.
These devices also have a Power-Failure Monitor that helps
to monitor an additional critical voltage on the Power-Fail
Input (PFI) pin. For example, the PFI pin could be used to
provide an early power-fail warning, detect a low-battery
condition, presence detection or simply monitor a power
supply other than +5V. The 1.25V threshold detector can be
adjusted using an external resistor divider network to provide
custom voltage monitoring of voltages greater than 1.25V,
according to Equation 1 (see Figure 2).
PFO goes low whenever PFI is less than the 1.25V (or
user-set) threshold voltage.
PFI V
DD
does not exceed its voltage threshold, reset is once
TH
POR
=
V
RST
RST
1.25
MR
DD
duration of 200ms. At any subsequent time that
R
-------------------- -
1
R
+
V
1V
2
TH1
R
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
2
FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)
7
t
POR
t
RPD
DD
and an
DD
(EQ. 1)
t
POR
.
If using a voltage divider on the PFI input to critique an
external voltage and intending to use the MR input to initiate
resets then avoid having the PFI voltage less than PFI Vth
+2.2V as unintended PFO transition may occur when MR is
transitioning high.
Adjusting t
On the ISL88707 and ISL88708, users can adjust the
Power-On Reset time-out delay (t
nominal t
between C
connecting a 50pF capacitor to CPOR will increase t
200ms to ~1.4s. Care should be taken in PCB layout and
capacitor placement in order to reduce stray capacitance as
much as possible, which contributes to t
FIGURE 2. CUSTOM V
POR
V
IN
POR
>t
MR
POR
of 200ms. To do this, connect a capacitor
and ground (see Figure 3). For example,
t
POR
R
1
R
2
TH
WITH RESISTOR DIVIDER ON PFI
PFI
POR
ISL8870x
) to many times the
POR
error.
January 12, 2009
POR
FN8092.5
from

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