X40011S8-AT1 Intersil, X40011S8-AT1 Datasheet - Page 11
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X40011S8-AT1
Manufacturer Part Number
X40011S8-AT1
Description
IC VOLTAGE MONITOR DUAL 8-SOIC
Manufacturer
Intersil
Type
Multi-Voltage Supervisorr
Datasheet
1.X40010S8-A.pdf
(24 pages)
Specifications of X40011S8-AT1
Number Of Voltages Monitored
2
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
2.9V, 4.6V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 10. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
Command Sequence?
Command Sequence
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
Complete. Continue
High Voltage Cycle
Continue Normal
Enter ACK Polling
by Issuing STOP.
Read or Write
Issue START
PROCEED
Returned?
ACK
YES
YES
11
NO
NO
X40010, X40011, X40014, X40015
Issue STOP
Issue STOP
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 13. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000
put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
H
and the device continues to out-
March 28, 2005
FN8111.0