X40415V8-B Intersil, X40415V8-B Datasheet - Page 11
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X40415V8-B
Manufacturer Part Number
X40415V8-B
Description
IC VOLTAGE MON DUAL W/SUP 8TSSOP
Manufacturer
Intersil
Type
Multi-Voltage Supervisorr
Datasheet
1.X40415V8IZ-B.pdf
(24 pages)
Specifications of X40415V8-B
Number Of Voltages Monitored
2
Output
Open Drain or Open Collector
Reset
Active High
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
1.3V, 2.6V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
Acknowledge Polling
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal high voltage cycle.
Acknowledge polling can be initiated immediately. To
do this, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
See Figure 12.
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address of the
address counter is undefined, requiring a read or write
operation for initialization.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. See Figure 13 for the
address, acknowledge, and data transfer sequence.
The disabling of the inputs during high voltage cycles
11
X40410, X40411, X40414, X40415
Figure 12. Acknowledge Polling Sequence
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The master
issues the start condition and the Slave Address Byte,
receives an acknowledge, then issues the Word Address
Bytes. After acknowledging receipts of the Word Address
Bytes, the master immediately issues another start con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an acknowledge from the device
and then by the eight bit word. The master terminates the
read operation by not responding with an acknowledge
and then issuing a stop condition. See Figure 14 for the
address, acknowledge, and data transfer sequence.
Command Sequence?
Command Sequence
Issue Slave Address
Byte (Read or Write)
Byte Load Completed
Complete. Continue
High Voltage Cycle
Continue Normal
Enter ACK Polling
by Issuing STOP.
Read or Write
Issue START
PROCEED
Returned?
ACK
YES
YES
NO
NO
Issue STOP
Issue STOP
March 28, 2005
FN8116.0