X40420S14I-A Intersil, X40420S14I-A Datasheet

IC VOLT MON DUAL SUP/SW 14-SOIC

X40420S14I-A

Manufacturer Part Number
X40420S14I-A
Description
IC VOLT MON DUAL SUP/SW 14-SOIC
Manufacturer
Intersil
Type
Multi-Voltage Supervisorr
Datasheet

Specifications of X40420S14I-A

Number Of Voltages Monitored
2
Output
Open Drain, Open Drain
Reset
Active High/Active Low
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
2.9V, 4.6V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
X40420S14I-A
Manufacturer:
Intersil
Quantity:
99
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
• Battery switch backup
• V
• Fault detection register
• Selectable power-on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
• 4Kbits of EEPROM
• Built-in inadvertent write protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
—Three standard reset threshold settings
—V
—Adjust low voltage reset threshold voltages
—Reset signal valid to V
—Monitor two voltages or detect power fail
V
(0.05s, 0.2s, 0.4s, 0.8s)
(25ms, 200ms, 1.4s, off)
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
—14 Ld SOIC, TSSOP
OUT
BATT
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
using special programming sequence
TRIP2
PRELIMINARY
: 5mA to 50mA from V
BATT-ON
(V1MON)
programmable down to 0.9V
V2MON
V
V
BATT
V
OUT
SDA
SCL
WP
CC
®
Decode Test
Command
1
& Control
System
Register
Battery
Switch
CC
Logic
Data
CC
= 1V
Data Sheet
; or 250µA from
V
CC
Logic
Monitor
1-888-INTERSIL or 1-888-468-3774
V2 Monitor
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Fault Detection
Logic
EEPROM
+
-
Register
Register
Status
Array
V
V
TRIP1
OUT
• Monitor voltages: 5V to 1.6V
• Memory security
• Battery switch backup
• V
APPLICATIONS
• Communications equipment
• Industrial systems
• Computer systems
X40420, X40421
DESCRIPTION
The X40420, X40421 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary supervision, manual reset, and Block
Lock
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
+
-
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Standard V
—Routers, hubs, switches
—Disk arrays
—Process control
—Intelligent instrumentation
—Desktop computers
—Network servers
V
TRIP2
V
OUT
OUT
2.9V(±1.7%)
4.6V (±1%)
4.6V (±1%)
Manual Reset
Reset Logic
Low Voltage
protect serial EEPROM in one package. This
All other trademarks mentioned are the property of their respective owners.
Generation
Watchdog
Power-on,
5mA to 50mA
May 25, 2006
Reset
|
and
Intersil (and design) is a registered trademark of Intersil Americas Inc.
TRIP1
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
Level Standard V
V
CC
OUT
activates the power-on reset
X40420, X40421
2.9V(±1.7%)
2.6V (±2%)
1.6V (±3%)
RESET
RESET
X40420
X40421
LOWLINE
4kbit EEPROM
MR
WDO
V2FAIL
TRIP2
Level Suffix
FN8117.1
-C
-A
-B

Related parts for X40420S14I-A

X40420S14I-A Summary of contents

Page 1

... CC Logic CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. X40420, X40421 4kbit EEPROM FN8117.1 Level Standard V Level Suffix TRIP2 2.9V(± ...

Page 2

... X40420V14I-B X4042 0VIB X40421V14I-B X40421V IB X40420V14IZ-B X4042 0VZIB X40421V14IZ-B (Note) (Note) X40420S14-A X40420S A X40421S14-A X40420S14Z-A X40420S ZA X40421S14Z-A (Note) (Note) X40420S14I-A X40420S IA X40421S14I-A X40421S IA X40420S14IZ-A X40420S ZIA X40421S14IZ-A (Note) (Note) X40420V14Z-A X4042 0VZA X40421V14Z-A (Note) (Note) X40420V14-A X4042 0VA X40421V14-A X40420V14I-A ...

Page 3

... EEPROM array with Intersil’s Block Lock protection. The array is internally organized The device features an 2-wire interface and software protocol allowing operation on a two-wire bus. The device utilizes Intersil’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Example Application Unreg ...

Page 4

PIN DESCRIPTION (Continued) Pin Name 6 RESET/ RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever RESET V falls below V CC grammed time period (t for t thereafter. PURST RESET Output. (X40420) ...

Page 5

PRINCIPLES OF OPERATION Power-on Reset Applying power to the X40420, X40421 activates a Power-on Reset Circuit that pulls the RESET/RESET pins active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. ...

Page 6

Figure 3. V Set/Reset Conditions TRIPX V TRIPX WDO 0 SCL SDA A0h Figure 4. Watchdog Restart .6µs 1.3µs SCL SDA Start WDT Reset V1 AND V2 THRESHOLD PROGRAM PROCEDURE (OPTIONAL) The X40420, X40421 is shipped with standard V1 and ...

Page 7

Resetting the V Voltage TRIPx To reset a V voltage, apply the programming volt- TRIPx age (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h ...

Page 8

Figure 6. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory ...

Page 9

BP: Block Protect Bit (Nonvolatile) The Block Protect Bits BP determines which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bit will prevent write operations to half the ...

Page 10

Figure 7. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the ...

Page 11

Figure 8. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indi- cate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During ...

Page 12

Figure 10. Byte Write Sequence Signals from the Master SDA Bus Signals from the Slave Page Write The device is capable of a page write operation initiated in the same manner as the byte write opera- tion; but ...

Page 13

Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal stop is issued in the middle of a data ...

Page 14

A similar operation called “Set Current Address” where the device will perform this operation if a stop is issued instead of the second start is shown in Figure 15. The device will go into standby mode after the stop and ...

Page 15

Figure 15. Random Address Read Sequence S t Signals from a the Master r t SDA Bus Signals from the Slave Figure 16. X40410/11 Addressing Slave Byte General Purpose Memory Control Register 1 0 ...

Page 16

ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C ...

Page 17

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Symbol Parameter (7) V Schmitt Trigger Input Hysteresis HYS • Fixed input level V • related level CC V Output LOW Voltage (SDA, RESET/ OL RESET, LOWLINE, V2FAIL, WDO) ...

Page 18

CAPACITANCE Symbol (1) C Output Capacitance (SDA, RESET, RESET/LOWLINE, OUT V2FAIL, WDO) (1) C Input Capacitance (SCL, WP) IN Note: (1) This parameter is not 100% tested. EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT ...

Page 19

A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time ...

Page 20

WP Pin Timing START SCL SDA IN t SU:WP WP Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a ...

Page 21

RESET/RESET/MR Timings V TRIP1 PURST t R RESET V RVALID RESET MR LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V) Symbol ( RESET/RESET (Power-down only) RPD1 TRIP1 LOWLINE RPDL ...

Page 22

Watchdog Time Out For 2-Wire Interface Start Clockin ( SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start 22 X40420, X40421 ...

Page 23

Programming Specifications: V TRIP1 TRIP2 Parameter t WDO Program Voltage Setup time VPS t WDO Program Voltage Hold time VPH t V Level Setup time TSU TRIPX t V Level Hold (stable) time THD TRIPX t V ...

Page 24

Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...

Page 25

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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