X5328V14 Intersil, X5328V14 Datasheet
X5328V14
Specifications of X5328V14
Related parts for X5328V14
X5328V14 Summary of contents
Page 1
... CC falls below a mini- CC trip point. RESET/RESET remains asserted returns to proper operating level and stabi- thresholds are TRIP RESET/RESET X5328 = RESET X5329 = RESET | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved ...
Page 2
... X5328 Z I X5329S8IZ* (Note) X5328V14* X5328V X5329V14* X5328V14Z* (Note) X5328V Z X5329V14Z* (Note) X5328V14I* X5329V14I* X5328V14IZ* (Note) X5328V Z I X5329V14IZ* (Note) X5328P-2.7A X5329P-2.7A X5328PZ-2.7A (Note) X5328P Z AN X5329PZ-2.7A (Note) X5329P Z AN X5328PI-2.7A X5329PI-2.7A X5328PIZ-2.7A (Note) X5328P Z AP X5329PIZ-2.7A (Note) X5329P Z AP X5328S8-2.7A X5328 AN X5329S8-2 ...
Page 3
... X5329S8IZ-2.7* (Note) X5329 Z G X5328V14-2.7* X5329V14-2.7* X5328V14Z-2.7* X5328V Z F X5329V14Z-2.7* (Note) (Note) X5328V14I-2.7* X5329V14I-2.7* X5328V14IZ-2.7* X5328V Z G X5329V14IZ-2.7* (Note) (Note) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
Page 4
PIN DESCRIPTION Pin Pin (SOIC/PDIP) TSSOP Name SCK RESET/ RESET 3-5,10-12 NC PIN CONFIGURATION 8 Ld ...
Page 5
PRINCIPLES OF OPERATION Power-On Reset Application of power to the X5328/X5329 activates a Power-on Reset Circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from start- ing to operate ...
Page 6
Figure 3. V Programming Sequence Flow Chart TRIP New V Applied = CC Old V Applied + Error CC Error ≥ Emax Emax = Maximum Desired Error Figure 4. Sample V Reset Circuit TRIP 4.7K V TRIP Adj. Program 6 ...
Page 7
... SPI SERIAL MEMORY The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years ...
Page 8
The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read ...
Page 9
Read Sequence When reading from the EEPROM memory array first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, ...
Page 10
Figure 6. Read Status Register Sequence CS 0 SCK SI High Impedance SO Figure 7. Write Enable Latch Sequence CS SCK SI SO Figure 8. Write Sequence SCK Instruction ...
Page 11
Figure 9. Status Register Write Sequence CS 0 SCK SI High Impedance SO SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be Will be steady steady May change Will change from LOW from LOW to HIGH to HIGH May change Will change ...
Page 12
ABSOLUTE MAXIMUM RATINGS Temperature under bias .................... -65°C to +135°C Storage temperature ........................ -65°C to +150°C Voltage on any pin with respect to V ...................................... -1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300°C ...
Page 13
EQUIVALENT A.C. LOAD CIRCUIT 2.06kΩ Output RESET/RESET 3.03kΩ 100pF A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing Symbol f Clock Frequency SCK t Cycle Time CYC t CS Lead Time LEAD t ...
Page 14
Serial Input Timing CS t LEAD SCK MSB IN High Impedance SO Serial Output Timing Symbol f Clock Frequency SCK t Output Disable Time DIS t Output Valid from Clock Low V t Output Hold Time HO ...
Page 15
Power-Up and Power-Down Timing V CC RESET (X5328) RESET (X5329) RESET Output Timing Symbol V Reset Trip Point Voltage, X5328-4.5A, X5328-4.5A TRIP Reset Trip Point Voltage, X5328, X5329 Reset Trip Point Voltage, X5328-2.7A, X5329-2.7A Reset Trip Point Voltage, X5328-2.7, X5329-2.7 ...
Page 16
V Set Conditions TRIP TRIP SCK Reset Conditions TRIP SCK > Programmed V CC TRIP 16 X5328, X5329 t THD ...
Page 17
V Programming Specifications V TRIP Parameter t SCK V Program Voltage Setup time VPS TRIP t SCK V Program Voltage Hold time VPH TRIP t V Program Pulse Width P TRIP t V Level Setup time TSU TRIP t V ...
Page 18
TYPICAL PERFORMANCE V Supply Current vs. Temperature ( -40C 25C Temp°C V vs. Temperature (programmed at 25°C) TRIP 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 18 X5328, X5329 t ) ...
Page 19
PACKAGING INFORMATION Half Shoulder Width On All End Pins Optional .073 (1.84) Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 19 X5328, X5329 8-Lead Plastic Dual In-Line Package Type ...
Page 20
PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20 X5328, X5329 Pin 1 0.014 ...
Page 21
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...