LP3881ESX-1.2/NOPB National Semiconductor, LP3881ESX-1.2/NOPB Datasheet
LP3881ESX-1.2/NOPB
Specifications of LP3881ESX-1.2/NOPB
Related parts for LP3881ESX-1.2/NOPB
LP3881ESX-1.2/NOPB Summary of contents
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... Shutdown Current (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accu- racy. Typical Application Circuit At least 4.7 µF of input and output capacitance is required for stability. © 2006 National Semiconductor Corporation Features n Ultra low dropout voltage ( Low ground pin current n Load regulation of 0.04%/ typical quiescent current in shutdown n 1.5% output accuracy (25˚ ...
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... Connection Diagrams TO-220, Top View Ordering Information Order Number Package Type LP3881ES-1.2 LP3881ESX-1.2 LP3881ET-1.2 LP3881ES-1.5 LP3881ESX-1.5 LP3881ET-1.5 LP3881ES-1.8 LP3881ESX-1.8 LP3881ET-1.8 LP3881EMR-1.2 LP3881EMRX-1.2 LP3881EMR-1.5 LP3881EMRX-1.5 LP3881EMR-1.8 LP3881EMRX-1.8 Block Diagram www.national.com 20063002 20063053 PSOP-8, Top View Package Drawing TO263-5 TS5B TO263-5 TS5B TO220-5 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Lead Temp. (Soldering, 5 seconds) ESD Rating Human Body Model (Note 3) Machine Model (Note 10) Power Dissipation (Note 2) V Supply Voltage (Survival) ...
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Electrical Characteristics over the full operating temperature range. Unless otherwise specified 4.7 µ (Continued) OUT S/D BIAS Symbol Parameter AC Parameters PSRR (V ) Ripple Rejection for Voltage PSRR Ripple ...
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Typical Performance Characteristics 4.7µF, S/D pin is tied 2.2V, V BIAS IN Dropout Temperature OUT Line Regulation vs V Unless otherwise specified 1.8V OUT 20063004 20063006 IN 20063008 ...
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Typical Performance Characteristics 4.7µF, S/D pin is tied 2.2V, V BIAS BIAS L Noise Measurement Line Regulation vs V www.national.com Unless otherwise specified 1.8V (Continued) OUT 20063010 20063014 BIAS ...
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Typical Performance Characteristics 4.7µF, S/D pin is tied 2.2V, V BIAS IN V PSRR IN V PSRR BIAS Unless otherwise specified 1.8V (Continued) OUT 20063020 20063022 7 = 25˚ 4.7µF, Cin ...
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... PNP or P-FET LDO regulator can cause a loss of phase margin which can result in oscillations, even when a Tantalum output capacitor is in parallel with it. This is not unique to National Semiconductor LDO regulators true of any P-type LDO regulator. www.national.com The reason for this is that PNP or P-FET regulators have a ...
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Application Hints (Continued) POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction tem- perature must be within the range specified under operating conditions. ...
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Application Hints (Continued) As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θ for the TO-263 package mounted PCB is 32˚C/W. Figure 2 shows ...
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Physical Dimensions inches (millimeters) unless otherwise noted TO220 5-lead, Molded, Stagger Bend Package (TO220-5) TO263 5-Lead, Molded, Surface Mount Package (TO263-5) NS Package Number T05D NS Package Number TS5B 11 www.national.com ...
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