DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 17

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
SCK1
PD3
SRD1
PD4
STD1
PD5
Notes:
Signal Name
1.
2.
3.
In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, the signal is tri-stated.
The Wait processing state does not affect the signal state.
All inputs are 5 V tolerant.
Input/Output
Input or Output
Input
Input or Output
Output
Input or Output
Type
Table 1-13.
State During
Ignored Input
Ignored Input
Ignored Input
Reset
Enhanced Serial Synchronous Interface 1 (Continued)
DSP56303 Technical Data, Rev. 11
1,2
Serial Clock—Provides the serial bit rate clock for the ESSI. The SCK1 is a
clock input or output used by both the transmitter and receiver in synchronous
modes or by the transmitter in asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half of
the serial clock.
Port D 3—The default configuration following reset is GPIO input PD3. When
configured as PD3, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SCK1 through the Port
D Control Register.
Serial Receive Data—Receives serial data and transfers the data to the ESSI
Receive Shift Register. SRD1 is an input when data is being received.
Port D 4—The default configuration following reset is GPIO input PD4. When
configured as PD4, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SRD1 through the
Port D Control Register.
Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD1 is an output when data is being transmitted.
Port D 5—The default configuration following reset is GPIO input PD5. When
configured as PD5, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal STD1 through the Port
D Control Register.
Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal Description
1-13