DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 3

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Features
Table 1 lists the features of the DSP56303 device.
Freescale Semiconductor
Internal Peripherals
High-Performance
Power Dissipation
Internal Memories
External Memory
DSP56300 Core
Expansion
Packaging
Feature
• 100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC),
• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals
• 192 × 24-bit bootstrap ROM
• 8 K × 24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
Program RAM
• Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address
• Program memory expansion to one 256 K × 24-bit words memory space using the standard external
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
• Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
• Very low-power CMOS design
• Wait and Stop low-power standby modes
• Fully static design specified to operate down to 0 Hz (dc)
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
• 144-pin TQFP package in lead-free or lead-bearing versions
• 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions
4096 × 24-bit
3072 × 24-bit
2048 × 24-bit
1024 × 24-bit
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
with skew elimination
test access port (TAP)
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
six-channel home theater)
are enabled
lines
address lines
dependent)
Size
DSP56303 Technical Data, Rev. 11
Table 1. DSP56303 Features
Instruction
Cache Size
1024 × 24-bit
1024 × 24-bit
0
0
X Data RAM
2048 × 24-bit
2048 × 24-bit
3072 × 24-bit
3072 × 24-bit
Size
Description
Y Data RAM
2048 × 24-bit
2048 × 24-bit
3072 × 24-bit
3072 × 24-bit
Size
Instruction
disabled
disabled
enabled
enabled
Cache
Switch Mode
disabled
disabled
enabled
enabled
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