DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 36

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
2-16
Notes:
No.
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Page mode cycle time for two consecutive accesses of the same
direction
Page mode cycle time for mixed (read and write) accesses
CAS assertion to data valid (read)
Column address valid to data valid (read)
CAS deassertion to data not valid (read hold time)
Last CAS assertion to RAS deassertion
Previous CAS deassertion to RAS deassertion
CAS assertion pulse width
Last CAS deassertion to RAS assertion
•
•
•
CAS deassertion pulse width
Column address valid to CAS assertion
CAS assertion to column address not valid
Last column address valid to RAS deassertion
WR deassertion to CAS assertion
CAS deassertion to WR assertion
CAS assertion to WR deassertion
WR assertion pulse width
Last WR assertion to RAS deassertion
WR assertion to CAS deassertion
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
1.
2.
3.
4.
5.
6.
BRW[1–0] = 00, 01—not applicable
BRW[1–0] = 10
BRW[1–0] = 11
The number of wait states for Page mode access is specified in the DRAM Control Register.
The refresh period is specified in the DRAM Control Register.
The asynchronous delays specified in the expressions are valid for the DSP56303.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, t
T
maximum value listed, as appropriate.
BRW[1–0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-
access.
RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t
C
for read-after-read or write-after-write sequences). An expression is used to compute the number listed as the minimum or
Table 2-9.
Characteristics
6
DRAM Page Mode Timings, Three Wait States
5
DSP56303 Technical Data, Rev. 11
Symbol
t
t
t
t
t
t
t
t
RHCP
t
t
t
t
t
t
t
t
WCH
RCH
t
RWL
CWL
WCS
ROH
t
CAC
t
OFF
RSH
CAS
CRP
t
ASC
CAH
RAL
RCS
t
t
t
t
WP
DH
GA
PC
AA
CP
DS
GZ
0.75 × T
4.75 × T
6.75 × T
1.25 × T
0.75 × T
2.25 × T
3.75 × T
3.25 × T
1.25 × T
Expression
0.5 × T
2.5 × T
4.5 × T
1.5 × T
2.5 × T
3.5 × T
2.5 × T
3.5 × T
2.5 × T
2 × T
3 × T
2 × T
4 × T
0.25 × T
3.5 × T
T
4 × T
C
—
− 4.0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
OFF
C
C
C
C
C
C
C
C
− 5.7
− 5.7
− 4.0
− 4.0
C
– 4.5
− 4.0
− 4.0
− 4.0
− 4.0
− 4.5
− 4.0
− 4.0
− 5.7
– 1.5
− 6.0
− 6.0
− 4.0
− 4.2
− 4.3
− 4.3
− 4.3
C
− 4.0
1,2,3
C
and not t
4
Freescale Semiconductor
GZ
Min
40.0
35.0
21.0
41.0
16.0
41.5
61.5
11.0
21.0
36.0
18.3
30.5
33.2
28.2
21.0
31.0
0.0
6.0
8.5
3.5
0.5
8.2
0.0
6.0
—
—
—
—
—
.
100 MHz
PC
Max
14.3
24.3
19.3
2.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
equals 4 ×
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—