DSP56303VL100 Freescale Semiconductor, DSP56303VL100 Datasheet - Page 58

• Manufacturer Part Number: DSP56303VL100
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56303VL100

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Package: 196MA-BGA
• Maximum Speed: 100 MHz
• Device Million Instructions Per Second: 100 MIPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Specifications
2.5.8
2-38
No.
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
Clock cycle
Clock high period
•
•
Clock low period
•
•
RXC rising edge to FSR out (bit-length) high
RXC rising edge to FSR out (bit-length) low
RXC rising edge to FSR out (word-length-relative) high
RXC rising edge to FSR out (word-length-relative) low
RXC rising edge to FSR out (word-length) high
RXC rising edge to FSR out (word-length) low
Data in set-up time before RXC (SCK in Synchronous mode)
falling edge
Data in hold time after RXC falling edge
FSR input (bl, wr)
FSR input (wl)
FSR input hold time after RXC falling edge
Flags input set-up before RXC falling edge
Flags input hold time after RXC falling edge
TXC rising edge to FST out (bit-length) high
TXC rising edge to FST out (bit-length) low
TXC rising edge to FST out (word-length-relative) high
TXC rising edge to FST out (word-length-relative) low
TXC rising edge to FST out (word-length) high
TXC rising edge to FST out (word-length) low
TXC rising edge to data out enable from high impedance
For internal clock
For external clock
For internal clock
For external clock
ESSI0/ESSI1 Timing
1
7
high before RXC falling edge
7
Characteristics
high before RXC falling edge
4, 5, 7
DSP56303 Technical Data, Rev. 11
Table 2-18.
2
2
2
2
2
ESSI Timings
Symbol
t
SSICC
Expression
2 × T
2 × T
1.5 × T
1.5 × T
3 × T
4 × T
C
C
- 10.0
− 10.0
C
C
C
C
9
Min
30.0
40.0
10.0
15.0
10.0
15.0
10.0
19.0
23.0
23.0
19.0
5.0
3.0
1.0
3.5
3.0
0.0
5.5
6.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100 MHz
Freescale Semiconductor
Max
37.0
22.0
37.0
22.0
39.0
37.0
39.0
37.0
36.0
21.0
37.0
22.0
29.0
15.0
31.0
17.0
31.0
17.0
33.0
19.0
30.0
16.0
31.0
17.0
31.0
17.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cond-
ition
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck s
i ck s
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns