TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 299
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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9. DMA Controller(DMAC)
9.1
Note 1: 1 word = 32 bits
Note 2: Following transfer type is not supported : From Peripheral circuit (register) to Peripheral circuit (register)
Function Overview
The table below lists its major functions.
Table 9-1 DMA controller functions
Number of channels 2ch (1 Unit)
Bus master
Priority
FIFO
Bus width
Burst size
Number of transfers
Address
Endian
Transfer type
Interrupt function
Special Function
Item
Hardware start
Software start
32bit × 1 (AHB)
(High) DMA ch0 to DMA ch1 (Low)
4word × 2ch
8/16/32bit
1/4/8/16/32/64/128/256
up to 4095
Transfer source ad-
dress
Transfer destination
address
Only little endian is supported.
Memory → peripheral circuit (register)
Peripheral circuit (register) → memory
Memory → memory
(note 2)
Transfer end interrupt
Error interrupt
Scatter/gather function
Function
incr / no-incr
incr / no-incr
Page 275
Supports DMA requests for peripheral IPs.
(Refer to Table 9-3)
Started with a write operation to the DMACx-
SoftBReq register.
Fixed by hardware
Settable individually for transfer source and
destination.
It is possible to specify whether Source
and Destination addresses should incre-
ment or should not increment (should be
fixed).
(Address wrapping is not supported.)
When "memory → memory" is selected,
hardware startup by DMA is not supported.
See the DMACCxConfiguration register for
more information.
Overview
TMPM362F10FG
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